01-23-2018 02:03 PM
I am working on Zynq simulation now, but I found it is not easy.
BFM can not used in Vivado 2017.
Is there any way I can run PS+PL simulation?
I want to verify DDR and AXI bus and evaluate the time delay within the whole process.
Any one can give me any hint?
Thanks a lot.
01-23-2018 11:35 PM
Zynq BFM will be replaced by Xilinx Zynq Verification IP in CY2017. For more information please contact your Local Xilinx Sales Contact.
Please check this videos and user guide for usage
02-02-2018 01:32 PM