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Visitor
Visitor
7,556 Views
Registered: ‎07-20-2015

Zynq7 DDR3 Modeling issue?

I've been running simulations for a DDR3-1067 bus. First off, I hope I'm using the correct models for the DDR3 bus since there are so many SSTL15 options available in the IBIS model.

 

I did come across a document that shows the DQ/CLK/DQS, DM all using 

 

SSTL15_T_DCI_F_PSDDR_O and SSTL15_T_DCI_F_PSDDR_IN40 

 

and the ADD/CNTL bus using SSTL15_S_PSDDR. 

 

I noticed that when using the SSTL15_T_DCI_F_PSDDR_O for the CLK, I get unusual delays between when the positive and negative sides transition, causing a very low crossing point and a violation of the VIX parameter in HyperLynx. This behavior occurs in all 3 corner cases. However, when I use the SSTL15_F_PSDDR model, I see the correct crossing of the signals in slow and typical, but I see a very low crossing in the fast case. Is there a modeling issue here??

 

The positive side is specified as the output, the negative side as a output inverted. I've set both the pos/neg to a diff pair in the IBIS model pointing to the correct model. 

 

I've attached the pics. 

SSTL15_F_PSDDR-fast.png
SSTL15_DCI_F_PSDDR_O-typical_fast_slow.png
SSTL15_F_PSDDR-typical.png
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Xilinx Employee
Xilinx Employee
7,521 Views
Registered: ‎07-31-2012

Re: Zynq7 DDR3 Modeling issue?

Hi,

 

Firstly you should understand what these models are.

 

SSTL15_T_DCI_F_PSDDR_O and SSTL15_T_DCI_F_PSDDR_IN40 are the models which use either the internal DCI termination (DCI) or the internal termination (IN40 model). In these cases, plese note that  you should not give an external termination for these respective pins. 

 

SSTL15_S_PSDDR - this is a simple model which does not use the internal termination and hence you would have to give an external termination based on the recommendation for the SSTL15 IO standard.

 

Once you have taken care of these, i guess you will have the correct wave forms and hence Vix. Let me know if you still have problems. One more recommendation is to use a simple model without the whole system as an initial check.

Thanks,
Anirudh

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Visitor
Visitor
7,475 Views
Registered: ‎11-10-2014

Re: Zynq7 DDR3 Modeling issue?

Thanks for the info. I was aware that those models had a digitially controlled impedance. However I'm still a little confused as to what the options are for this device when using a DDR3 interface.

 

The thread said to use the DCI PSDDR O and DCI PSDDR IN40 models for the CLK/DQS/DQ/DM, and SSTL15_S_PSDDR model for the ADD/CNTL signals.

 

Are there other options available for this device, or is this all that can be used when configuring it for DDR3? Please understand that I am only doing the signal integrity/ timing analysis for this bus. I don't have the board, chip, or software in front of me to configure it. 

 

From what I take from your message, if using the DCI type models, there should be no external termination? We have 80.4 Ohms differential external termination on the CLK currently.

 

Please let me know ASAP, since I need to provide feedback to the PCB designer. Thanks again for the info. 

 

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Xilinx Employee
Xilinx Employee
7,449 Views
Registered: ‎07-30-2007

Re: Zynq7 DDR3 Modeling issue?

This looks like a modeling issue- there should not be a large time delay between the launch times.

 

Can you confirm you are using the latest IBIS models? I believe 2.2 is the latest version.

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Visitor
Visitor
7,441 Views
Registered: ‎11-10-2014

Re: Zynq7 DDR3 Modeling issue?

I just checked and noticed that the version says 2.1 from Sep of 2013..... I will download the newest version and see if that problem is fixed.

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Visitor
Visitor
7,434 Views
Registered: ‎11-10-2014

Re: Zynq7 DDR3 Modeling issue?

I downloaded the newest model (2.2) and the Vix problem appears to be fixed. All three corner cases look good now. 

 

Thanks again!

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