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Explorer
Explorer
2,474 Views
Registered: ‎07-29-2009

access to continuous clock for SPI bus

I was reading this and wanted to do something similar:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-connect-PS-SPI-peripheral-through-EMIO-with-external-device/m-p/600394#M7321

 

But, I think the spi clk only runs when data is present.  Is there another clock to use to run exterior logic with that runs continuously that is the same rate as the spi clk available?

Kurt

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Moderator
Moderator
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Registered: ‎07-31-2012

Hi,

 

For external logic you may want to try using fabric clock from PS to PL.

 

Regards

Praveen


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Explorer
Explorer
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Registered: ‎07-29-2009

You're right, but the SPI clock could be any rate, and not just the fabric clock from the PS, right?

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Community Manager
Community Manager
2,399 Views
Registered: ‎07-23-2012

SPI clock frequency can. E set in Zynq processing system IP gui to a fixed value. If you set it to say 100 MHz, you can set one of FCLKs to the same frequency-100MHz.
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Explorer
Explorer
2,386 Views
Registered: ‎07-29-2009

Under clock configurations, my SPI clk is 166 MHz.  I know that's NOT the spi clock for peripherals since I've measured them on an o-scope. As a matter of fact, the data sheet says the EMIO and MIO SPI clocks are limited to 25 and 50 MHz respectively. Where else is the SPI clk rate set?

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Scholar
Scholar
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Registered: ‎04-13-2015

The SPI clock is derived from the controller clock with the divider in the config register.

ug585 Zynq's TRM in Appendix B

That's the BAUD_RATE_DIV bits (5:3) and it can only divide by 4, 8, 16, 32, 64,128 and 256.

You could use an external divider but it will most likely not be synchronized with the bus clock the SPI controller generates.

Also to consider is if the controller reset its internal divider before a transaction.

 

 

 

 

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