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Visitor
Visitor
394 Views
Registered: ‎06-19-2019

add custom module to IP block design error

Hello everyone.

I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs'

image.png.e05f09f81487c508cf6453109a952737.png

and now, I tried to use custom counter module by Verilog.


module clock_divider(
    input clk,
    input [4:0]key,
    output reg [7:0]led
    );
      //we will need one register to keep the clock count number;
  reg [22:0] count;
      
      
         always @(posedge clk)        // judge the clk rise edge;
            if (key) begin            // if the key has been pressed,
               if(count==0) begin     // then count value flip over to zero, then make led on or off
                  led <= ~led;        // in the always loop, it needs to use registers
               end
               count <= count +1;     // add the count value until it flips over to zero
            end 
            else 
               begin            // if there is no key to be pressed, init the led to off state;
               led <=0;
               count <=1;
               end


endmodule

and I included this module in IP design.

image.thumb.png.c6f01e7aa78d4ac13ff6edf92d03044a.png

and the errors were like below.

image.thumb.png.12329fc516b3bb4d756c19ec9bb19084.png

before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed'

I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? 

Thank you for your kind answers,

...

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2 Replies
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Scholar
Scholar
336 Views
Registered: ‎02-01-2013

 

It's generally good practice to resolve warnings and critical warnings before they can become troublesome. Investigate each of the Critical Warnings reported in the Messages pane, and resolve them (or dismiss them) before moving to the next FPGA-generation step.

That aside, your clock_divider module needs work. Do led and key really need to be vectors?

Also: you've got two inputs tied together, with no driver.

2019-10-14_14-08-27.jpg

-Joe G.

P.S. FWIW: Something I find unkempt is the simultaneous use of axi_gpio_0/GPIO as an external interface and as an input for internal connections. I would use two different GPIO ports, in such a case.

2019-10-14_14-08-27.jpg

 

 

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Highlighted
Visitor
Visitor
298 Views
Registered: ‎06-19-2019

thank you.. someone said that led constraints conflict with GPIO-LED.

and I tried another module without sw, led and succeed. 

thank you.

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