cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
413 Views
Registered: ‎01-07-2019

axi_DMA Problems with HLS IP core and Zynq PS

Hi all!

I am currently developing a complete image processing project with OpenCV, HLS, Vivado and SDK libraries. The entire project is based on connecting two HLS IPs through an AXI-Stream interface, and in turn connecting them to the Zynq processing system.

I work with a Zybo z7 based on zynq 7010. The version I use of Vivado is 2018.2.

For the development of the work, I have started testing with only one of the two designed IPs. This has the function of passing a grayscale image and quantifying its values ​​below a limit (simple tasks). The IP input is a 32-bit axiStream (4-channel image) and the output is an 8-bit axiStream (1 channel).

This IP is linked to the processing system through an AXI-DMA. After that, in SDK, following several tutorials, I designed a code to try to send the image and receive the quantified image. During its execution, the program stops in the XAxiDma_Busy () function for an infinite time.

I have read numerous forum posts on this topic, most of it is concluded that this happens due to problems with the size of the data sent, or problems with the t_valid signal of the IP. Both issues are a problem, since, as the program fails, I am not sure that you are doing things correctly.

Regarding the t_valid signal, in HLS I use the following directives in relation to the axi ports:

#pragma HLS INTERFACE axis port=input_axistream
#pragma HLS INTERFACE axis port=output_axistream

//#pragma HLS INTERFACE s_axilite port=threshold_factor bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS

With them, the AXI signals in are joined in a single control bus, whose union with the rest of the elements in the block diagram is done automatically. The commented line related to axiLite is used when I add some configuration parameters. If I do not put the other line related to the control bus, when I create the IP, I have several unconnected signals that do not connect automatically, and I don't know what to do with them.

I add a photo of the IP block with the single bus line, and another without it.

My first question is to know what I should do with these signals, and if I can operate the system through this control bus. In the library that creates SDK to use IP, there is a Start function. When I use it, the program remains stopped during its execution, and does not recover. I don't know if I should start the operation of the IP in any special way, and I don't know if I should do it in a SW or HW way. In addition, all this I want to apply also to a second IP that will be connected to this first IP in the future, so I want to understand how it is done.

Regarding the issue of data sent and received:

First, I use a code to put an image into a variable in C:

I = imread("2_tb_final_0.bmp", IMREAD_COLOR); 
int pixel = 0;
int p0 = 0;
int p1 = 0;
int p2 = 0;

for (int j = 0; j < I.rows; j++)
{
   for (int i = 0; i < I.cols; i++)
   {
      unsigned char* p = I.ptr(j, i); // Y first, X after
     pixel = (p[2] << 16) + (p[0] << 8) + p[1];
     p0 = p[0];
     p1 = p[1];
    p2 = p[2];
    cout << pixel << ",";
   }
}

In this way I get an array of 32-bit values, which have the information of the colors of the pixels placed so that the IP can understand it. My first question is whether this process is well carried out.

After that, I send the data to the DMA through two buffers (as I have seen in tutorials). I have left my code attached in the post, and I wanted to know if I do this procedure well. During this process you have to perform several casts and I don't know if at any time I am making mistakes with the size of the data or something similar.

My last question comes from the DMA configuration. In my case, I have a 32-bit data input, and an 8-bit output. I do not know how to configure this block and the subsequent SDK code so that there is agreement between the length of data read and sent.

It is currently configured for 32-bit sending, when it receives, will the data also come in 32-bit variables? Or will 4 8-bit packets come in a variable of 32? Or how this works exactly.

Thank you very much for the attention, I feel the extension, but I did not know how to explain all my problem without giving so many details.

A greeting!

0 Kudos
1 Reply
Highlighted
Visitor
Visitor
411 Views
Registered: ‎01-07-2019

Re: axi_DMA Problems with HLS IP core and Zynq PS

I add too my code from HLS:

0 Kudos