recently i met a problem about axi-3 write operation ,the question is:
i send some axi burst frome pl to ps ,and find the wready is low during the debug process.
some information :
in pl ,i receive ethernet frames ,and divide it into several axi-busrt (in order to meet the axi-3 proctol),the awlen of these bursts are different(1~16); and i do some axi write operations to send these burst to ps;
ps : i use an axi data width converter ip to intercontact the s-axi interface and the m-axi-interface is connected to the hp port