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pruthvi_8889
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Registered: ‎12-05-2012

axi external slave connector address is unmapped

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Helo guys,

I have connected an axi external slave connector to an axi interconnect but I donno why the address in unmapped I tried to generate the address it says address generated succesfully but still it says the address is unmapped any reason for this and I want to write a C application for it in sdk and I cant find the parameters/address for the axi external slave connector.

 

Please help me with this.

 

I have also attached my address settings below

 

addressmap_zynq.bmp
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dchavir
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Registered: ‎05-12-2011

There are a million ways to accomplish what you want to do, the trick is first thinning out the choices to a manageable quantity then make a choice and go for it.  If you're not all that familiar with the whole AXI interface between the PS and PL, my main suggestion is don't try to create a 3-channel combining BRAM to DDR DMA transfer mechanism as your first attempt.  Start small with some dummy data in one BRAM and get that moved to DDR.  Once you have mastered that, you will have learned quite a bit, and can then expand the design and test again.  If you iteratively increase the complexity in steps that allow you to fully understand how everything is working, you will eventually arrive at the best way to implement your required design.  If you try to do too much before you really understand all of the interworkings of things though, you will just end up frustrated.

 

A simple overview of what I think you're trying to do, in very bad ASCII art, might be:

 

DDR <-- PS AXI HP Slave <-- (some sort of logic, CDMA, custom, whatever) <-- BRAM <-- (logic that feeds the BRAM)

 

Presumably you're looking for a way to move the data you've collected in the BRAM into DDR so the processor can do something with it, without requiring the processor to sit and read 4 or 8 byte chunks at a time.  DMA is the generic way to do this, but as you may have noticed the CDMA can be a complicated little beastie.  Perhaps you would be better off writing custom logic for the center piece that reads the BRAMs and stuffs the data into the PS AXI HP Slave interface directly.  If you want to eventually expand to three BRAMS/channels, that might be a good way to go.  If the data is streaming, meaning it's always coming in and you just need to let the processor know when one full frame or set of data has arrived, then you wouldn't really need a control slave interface (master from the PS) to set up transfers, you could just use a circular buffer arrangement of some sort in DDR and hope the CPU can keep up.

 

If you begin by just getting some PL logic to stuff data into DDR through the PS AXI HP Slave port, even if it's just one frame of test pattern data, you should be well on your way.

 

Cheers,

-Doug

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dchavir
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Registered: ‎05-12-2011

Are you certain you want an external slave?  My understanding is that's for use in connecting IP that's completely external to the EDK project.  It sounds like you may want a regular AXI4-Lite slave instead, I've never seen a regular AXI4 slave end up in the unmapped addresses category.

 

In looking at the address assigned as shown in your attachment, it looks like the address is a 64k chunk of your DDR memory.  Perhaps this indicates that an external slave interface means there's expected to be some external master IP that will be reading/writing that 64k chunk of memory with no intervention on the part of the embedded system.  Is that what you're after?

 

Cheers,

-Doug

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pruthvi_8889
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Registered: ‎12-05-2012

Hello Doug,

 

Thanks for your reply.

I would like to interface my vhdl module which collects data from dual port rams and need to write it on the ddr3 ram. Hence, I felt the need of a external slave connector.

 

But I cant understand the problem

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pruthvi_8889
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Registered: ‎12-05-2012

Hello Doug,

 

Please have a look at the attached bus address for better understanding

 Also the drc check is successful

 

 

addrs.JPG
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dchavir
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Registered: ‎05-12-2011

I guess I don't understand why you're using the external AXI interface in the first place, other than apparently someone else said they did.  As far as I can see, the external slave interface gives a master access to DDR, which you already have through the normal AXI HP interface (AXI CDMA in the PL is the master, PS slave interface can be mapped to wherever you like in DDR), so why then add another external interface?

 

Have you studied the example in ug873 that sets up a DDR to DDR transfer scheme?  That's basically what you want to do, only instead of connecting both of the CDMA ports back to the HP AXI interconnect, you would only connect one of them there and then connect the other to your BRAM.  This of course means you're going to need an AXI interface on your BRAM, lucky for you there's an AXI BRAM interface that looks like it will do the trick for you.

 

What it looks like you want, is an AXI BRAM interface (slave), connected to one master port of the CDMA.  The other CDMA master port then gets connected to one of the HP slave interfaces in the PS, and you wire up a GP PS master interface to the register slave interface in the CDMA for control and status.  That should be it, assuming you can stuff the BRAM from your VHDL.  I haven't looked at the AXI BRAM IP so I don't know what it has as far as dual port BRAM capability goes.  But in any event, I don't see a need for an external AXI slave interface into DDR.

 

If I were you, I would build the example from ug873, then hack on it to customize it from there.

 

Cheers,

-Doug

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pruthvi_8889
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Registered: ‎12-05-2012
Actually I am working on the example of ug873 but my problem is I have 3 dual port RAMS and I need to combine the data and write in to ddr3 ram.
I am very begginer so what would you suggest in my case ??
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dchavir
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Registered: ‎05-12-2011

There are a million ways to accomplish what you want to do, the trick is first thinning out the choices to a manageable quantity then make a choice and go for it.  If you're not all that familiar with the whole AXI interface between the PS and PL, my main suggestion is don't try to create a 3-channel combining BRAM to DDR DMA transfer mechanism as your first attempt.  Start small with some dummy data in one BRAM and get that moved to DDR.  Once you have mastered that, you will have learned quite a bit, and can then expand the design and test again.  If you iteratively increase the complexity in steps that allow you to fully understand how everything is working, you will eventually arrive at the best way to implement your required design.  If you try to do too much before you really understand all of the interworkings of things though, you will just end up frustrated.

 

A simple overview of what I think you're trying to do, in very bad ASCII art, might be:

 

DDR <-- PS AXI HP Slave <-- (some sort of logic, CDMA, custom, whatever) <-- BRAM <-- (logic that feeds the BRAM)

 

Presumably you're looking for a way to move the data you've collected in the BRAM into DDR so the processor can do something with it, without requiring the processor to sit and read 4 or 8 byte chunks at a time.  DMA is the generic way to do this, but as you may have noticed the CDMA can be a complicated little beastie.  Perhaps you would be better off writing custom logic for the center piece that reads the BRAMs and stuffs the data into the PS AXI HP Slave interface directly.  If you want to eventually expand to three BRAMS/channels, that might be a good way to go.  If the data is streaming, meaning it's always coming in and you just need to let the processor know when one full frame or set of data has arrived, then you wouldn't really need a control slave interface (master from the PS) to set up transfers, you could just use a circular buffer arrangement of some sort in DDR and hope the CPU can keep up.

 

If you begin by just getting some PL logic to stuff data into DDR through the PS AXI HP Slave port, even if it's just one frame of test pattern data, you should be well on your way.

 

Cheers,

-Doug

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