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Adventurer
Adventurer
1,652 Views
Registered: ‎11-27-2010

axi intc [behind GIC], interrupt + axi message

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Hi,

    I have a vivado design with axi intc behind a gic

 

 Custom ip block [axi lite] 16 interrupts --connected-->  AXI INTC's --> concat --> one of the PS-PL port of 16 IRQ

 

in the above diagram, i wanted to understand how interrupt signals reach out to processor.

 

interrupt is a single bit pulse which reaches out to CPU and how does CPU knows which interrupt is being set?. is it via running through 0x0 to 0xC registers in memory space.

 

in this regard, i believe following is happening, please confirm/correct

there are 2 message sent out by custom ip block [interrupt [single bit pulse] and axi lite message]?

 

From axi intc manual: -

In normal interrupt mode, the IAR is cleared by the acknowledgment received over the AXI interface

 

        1. i want to understand what is the message sent over the axi interface and the corresponding acknowledgement received over the axi interface.

        2. i tried understanding from various documents [axi intc, GIC and axi manual] and could not understand how CPU process interrupt and understand which INPUT pin/port of intr is PULSE'd in and only one bit pin i.e. irq is OUTPUT out of axi intc and calls corresponding interrupt handler.

 

                Is it via reading the 0x0 to 0xc register in that particular axi intc memory mapped region?

                or

                Is it via axi lite message received, CPU comes to know about the interrupt handler to be called?

 

               what if there are more axi intcs connected behind GIC, how does cpu process those interrupts and calls appropriate interrupt handler.

 

        if you know any doc, which explains these in detail, please point me to them.

 

 

Thanks

 

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Xilinx Employee
Xilinx Employee
1,706 Views
Registered: ‎10-04-2016

Hi @optivareddy,

Latency to service interrupts can certainly be an issue, particularly if you are running under an operating system.

 

I'd argue that this issue is not unique to the Zynq US+ architecture; it's a reality of embedded system design. You would need to look at the full range of options in hardware and software to mitigate the time it takes to service an interrupt.

 

Regards,

 

Deanna

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Xilinx Employee
Xilinx Employee
1,599 Views
Registered: ‎10-04-2016

Hi @optivareddy,

Once the processor receives the interrupt and determines it has come from the AXI INTC, it will issue an AXI read to the Interrupt Status Register in the AXI INTC IP via the AXI Lite interface. This is how the processor discovers which interrupt to the AXI INTC has fired and then jumps to the corresponding ISR.

 

This Wiki page discusses Xilinx's support for the AXI INTC. 

http://www.wiki.xilinx.com/Cascade%20Interrupt%20Controller%20support%20in%20DTG

 

The Zynq US+ TRM discusses how the PL-PS interrupts map to the GIC. Please refer to Chapter 13.

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

 

Regards,

 

Deanna

 

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Adventurer
Adventurer
1,590 Views
Registered: ‎11-27-2010

Hi Deanna,

                Excellent, Thanks for reply.

 

one more question

 

1. So latency is not an issue in such cases? I meant, about axi read operation and then returned axi msg which carries the value of the register.

 

trigger pulse -> cpu recognizes its axi intc -> issues axi read -> gets back axi reg value -> reads axi reg -> raises interrupt handler.

 

so there are atleast 4 operations between PULSE and interrupt handler, so my question is

 

this latency is not a concern ?

 

Thanks

  

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Xilinx Employee
Xilinx Employee
1,707 Views
Registered: ‎10-04-2016

Hi @optivareddy,

Latency to service interrupts can certainly be an issue, particularly if you are running under an operating system.

 

I'd argue that this issue is not unique to the Zynq US+ architecture; it's a reality of embedded system design. You would need to look at the full range of options in hardware and software to mitigate the time it takes to service an interrupt.

 

Regards,

 

Deanna

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