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Registered: ‎03-05-2020

axi master module writen by myself cannot communicate with axi interconnect

    I write two axi master module to communicate with a memory by axi interconnect, but it does not work( a master can mightly write memory, but another master donot  work when read the memory because the bvalid signal doesnot come through the crossbar).  I think the first master may not finish its write transaction.

   There are two cases I donot understand..

   First, the wlast works good at  s00_coupler's slave interface. But it does not reset at  s00_coupler's master interface, it comes to 0 only when the next transaction comes.(show in figure 2)

  Second, the bid signal is right when the transaction occurs, but the bid signal show up again after several transaction.(show in figure 3)

  Do I misunderstand the axi protocol(my master module can commubicat with memory directly) or configure the axi interconnect wrong? I will appriciate your answer. Thanks! 

topology.PNGwlast.pngbid casebid case

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