02-15-2021 09:49 AM
I am using an axi_mem_intercon to access 2 separate DDR4_SDRAM(MIG) on the master side the save side has a XDMA to access both memories a state machine to read from one of the DDR4s and a stat machine to write to the other DDR4. It will work fine for hours, then will fail. What I am seeing is normally the AXI signals coming out of the interconnect follow the signals going in by several burst cycles. When it fails the AXI signals look correct going into the interconnect but coming out the address and data are out of sync. Address goes out to the ddr4 correctly, but it appears that the data is from the next burst cycle. It appears tht the data is lost for one burst cycle.
Also can the xdma be connected to 2 separate axi_mem_interconnects? I was not able to connect them in the Block design.
02-19-2021 04:52 AM
That's not really much to go on, nor is it enough to find a bug with.
It sounds like you are using a custom AXI master. Let's start there then. Care you share your AXI master logic with us? Can you connect your design to an AXI VIP to look for potential AXI errors? Have you formally verified your AXI master to make sure there are no errors within it? Can you provide a trace showing an example of whatever error it is that you are struggling with?
All of these will go a long way to helping us help you.
02-19-2021 12:05 PM
I have an AXI Protocol checker on the custom AXI Master and it does not see any errors. I have attached a doc with some timing diagrams from the iLA. The first section shows good data going into the interconnect. The second section shows the delay of the data thru the interconnect. The third section showed the details of the data coming out of the interconnect. The address does not show the MSB but you can see tht the data for address C0000000 on the output side is not the same as on the input side. It is actually the data for the next burst of data.