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Adventurer
Adventurer
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Registered: ‎04-12-2020

axi stream T valid

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Hello everyone

i have a small question regarding AXI stream protocol, Is it legal to assert Tvalid signal to '1' all the time or are there any strict timing requirements on T valid signal?. I have a stream of data which i want to transfer to axi stream slave in frames, I assert T last signal on the last packet of frame, is it necessary to deassert T valid signal as well after the last packet is sent to slave or T valid can stay high?

Thanks in advance

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Observer
Observer
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Registered: ‎07-09-2018

It is not mandatory to deassert TVALID if the data you want to continue sending data to slave after the TLAST. From your example I understand that you want to send new data immediatly after the TLAST? In this case, I cannot see any reason why TVALID have to be deasserted and can continue to be high (1) in accordance to the AXI-Stream protocol.

Mathieu.

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Observer
Observer
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Registered: ‎07-09-2018

In the AXI-Stream protocol, a data is asserted only when TVALID and TREADY is high. If you transaction is done, you should  deassert TVALID (TVALID = 0). Your code should always assume that TREADY could change at any time. Also, when TVALID is high (1) and TREADY is low (0), TVALID shoudl stay asserted until TREADY is high. Only then the data is asserted to the slave. Here is a quick diagram to sghow you what I mean.

 

axis.jpg

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Adventurer
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Registered: ‎04-12-2020

@mathieu20 

thanks for reply, i understand to transfer data , both tvalid and tready needs to be high. My question was after the last packet when t last is asserted, is it compulsory to deassert Tvalid signal according to AXI specs, i could not find exact answer there, from your answer it seems that it is mandatory to deassert Tvalid signal and then assert again for another frame.

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Observer
Observer
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Registered: ‎07-09-2018

It is not mandatory to deassert TVALID if the data you want to continue sending data to slave after the TLAST. From your example I understand that you want to send new data immediatly after the TLAST? In this case, I cannot see any reason why TVALID have to be deasserted and can continue to be high (1) in accordance to the AXI-Stream protocol.

Mathieu.

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Adventurer
Adventurer
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Registered: ‎04-12-2020

@mathieu20 

ok thanks, that solved the confusion, I am little bit confused about one thing, once the tvalid signal is asserted, it cant be deasserted if the ready signal is low, Tvalid signal can only be deasserted if the ready signal from slave is high, did i understood correctly, Ready signal from AXI DMA core changes with different burst sizes hence confusion.

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Scholar
Scholar
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Registered: ‎05-21-2015

@MuzamilFarid,

  1. TVALID may not be fixed to a constant 1.  It must be set to zero following !ARESETN.  As @mathieu20  pointed out, other than that it may remain asserted as long as you have additional data to send.
  2. TVALID may be deasserted following TREADY.  It must be deasserted following !ARESETN.  Otherwise, it may *not* be deasserted following TVALID && !TREADY.
  3. Be aware of Vivado's auto-generated AXI stream master.  Yes, that one is broken as well.  In particular, TLAST might change following TVALID && !TREADY when using that core--in violation of the protocol.
  4. You should also know that the AXI S2MM core has some surprises in it.  Be careful not to feed it any data before configuring it.  Also, beware that TLAST will terminate a transaction even if the word count hasn't yet completed.

Hopefully that set's you back on your feet,

Dan

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Adventurer
Adventurer
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Registered: ‎04-12-2020

@dgisselq 

i didnt understand what you meant, AXI protocol works on active low reset, you mean that the Tvalid signal should be de asserted after the reset is activated?

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Scholar
Scholar
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Registered: ‎05-21-2015

@MuzamilFarid,

Here's the relevant specification,

axi-reset-spec.png

So, to answer your question, TVALID should be deasserted on the clock following aresetn being asserted (i.e. low).  (Since it's negative logic, I consider the reset being asserted to be when it is low, and deasserted to be when its high--it seems like the spec disagrees with this terminology however.)  Although this is taken from an AXI4 spec, the stream spec is (roughly) the same.  "During reset, TVALID must be driven LOW."  and again,j "A master interface must only begin driving TVALID at a rising ACLK edge following a rising edge at which ARESETn is asserted HIGH."--then they show roughly the same figure as I copied above.

Dan

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Adventurer
Adventurer
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Registered: ‎04-12-2020

@dgisselq 

thanks for clarification, i understand now completely.

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