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younggeun
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Registered: ‎12-21-2020

axi4 read rvalid held high problem.

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I implemented axi-master.

this axi-master signals are connected with axi interconnect slave and these are for read only.

this axi interface is for reading the data from mig(ddr4).

i am driving the axi-master by state machine. burst length is 4, the read data width is 256bit.

but when read transfer starts, rvalid signal keeps high, rlast & rready are normal. 

once read transfer starts, rvalid never come to low. and also axi master access to somewhat wrong ddr address..

younggeun_0-1618221609580.png

 

other signals are as below.

axi_m_arburst = 2'd0;
axi_m_arcache = 4'd0;
axi_m_arid = 2'd0;
axi_m_arlock = 1'b0;
axi_m_arprot = 3'd0;
axi_m_arqos = 4'd0;
axi_m_arregion = 4'd0;

axi_m_arlen = 8'd3;
axi_m_arsize = 3'd5;
axi_m_arburst = 2'd1;

[31:0] araddr is incremented + 32'd128;

 how can i solve this problem??

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dgisselq
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Registered: ‎05-21-2015

@younggeun ,

I notice you are checking for RLAST without also checking for RVALID at the same time.  RLAST is properly a don't care value unless RVALID is also true.  This is a bug.

Dan

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dgisselq
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Registered: ‎05-21-2015

@younggeun ,

Your trace shows RVALID going low.  I'm not sure I understand your problem.  RLAST isn't going low, but then again RLAST is a don't are if RVALID isn't also high on the same cycle.

Dan

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younggeun
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Registered: ‎12-21-2020

I was wrong with different ILA capture. I've just uploaded it properly.

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dgisselq
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Registered: ‎05-21-2015

@younggeun ,

From your updated capture, it looks like you are holding RREADY low for one burst, and so your RREADY is perpetually behind.

Can you share your custom AXI master design with us at all?  That might help us find the bug ...

Dan

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younggeun
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Registered: ‎12-21-2020

thank you for reply. the state machine is as below.

sts_0 : begin // the master must not wait for the slave to assert ARREADY before asserting ARVALID
// loading read address
// read axi control signal setting
o_axi_m_araddr <= ddr4_base_addr + rd_addr; // new address update
o_axi_m_arvalid <= 1'b1; //read address valid
o_axi_m_arid <= 2'd0;
o_axi_m_arlen <= 8'd3; //burst length : 4
o_axi_m_arsize <= 3'd5; // burst size : 256/8bit = 32byte
o_axi_m_arburst <= 2'd1; // burst type : increment
next_sts <= sts_1;
end


sts_1 : begin //arready status check
cnt_data_frame <= 2'd0;
if(i_axi_m_arready) begin //minimum araddr 1clk + arready 1clk(when arready is low for starting)
next_sts <= sts_2;
o_axi_m_arvalid <= 1'b0; //read address valid clear
end
else begin
next_sts <= sts_1;
end
end


sts_2 : begin // axi control signals are cleared.
o_axi_m_arvalid <= 1'b0; //read address valid clear
o_axi_m_arid <= 2'd0; // id clear
o_axi_m_araddr <= 32'd0; // address clear
o_axi_m_arlen <= 8'd0; //burst length clear
o_axi_m_arsize <= 3'd0; // burst size clear
o_axi_m_arburst <= 2'd0; // burst type clear

o_axi_m_rready <= 1'b1; // ready for receiving the read data!!!!!!!
if(i_axi_m_rvalid & ~i_axi_m_rlast) begin // read data valid high status
next_sts <= sts_2;
end
else if(i_axi_m_rlast) begin // last data timing
o_axi_m_rready <= 1'b0; // rready clear;
next_sts <= sts_3;
end
else begin
next_sts <= sts_2;
end
end

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dgisselq
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173 Views
Registered: ‎05-21-2015

@younggeun ,

I notice you are checking for RLAST without also checking for RVALID at the same time.  RLAST is properly a don't care value unless RVALID is also true.  This is a bug.

Dan

View solution in original post

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