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Registered: ‎02-11-2019

bitstream error

Hello..

I am using ilinx vivado 2016.3 . MYC-Y7z020 SOM i am using.

in my design i have two ethernets for that i am using gmii-to-rgmii ip and one mre ip i am using axi ethernet subsytem for both i selcetd shared logic in core . i am getting below DRC error please Help me with this

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

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