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vooalals
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Registered: ‎09-30-2014

bug in zynq spi(ps) controllers

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zynq spi(ps) controller is configured as:

1. master mode;

2. clock polarity => 0;

3. clock phase => 0;

when a new transfer is started, the ss(slave select) pin and clk pin are set to 0 at the same time, which will probably result in a metastability from the slave's view because clk should be inactive when ss is asserted.

i think clk should be set to 0 before ss is asserted to remove metastability.

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vooalals
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Registered: ‎09-30-2014

 

xra1405(the slave) captures input bits[0:n] at rising edges and primes output bits[1:n] at falling edges. i think it is not innocent with this issue because it should only response to falling edges after the first rising edge.

 

you are right, there's no standard document.
thanks a lot for your help.

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trenz-al
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Registered: ‎11-09-2013

how did you measure SAME time???

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vooalals
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Registered: ‎09-30-2014

i watched the signals using a oscilloscope.

if there's no garbling, delay between the two signals at falling edge is less than 1ns. or clk signal even falls a few ns later.

 

for my application, a xra1405(spi slave/pol@0/pha@0) is used, this slave works unsteadily with zynq spi(ps) controller due to this issue.

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trenz-al
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Registered: ‎11-09-2013

well if look signals going through fabric and iob with scope you do not see the real timing a the PS7 block output.

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vooalals
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Registered: ‎09-30-2014

then i suggest xilinx to check your ps7 spi output by yourself please.

my spi system clock is about 166 Mhz, bus data rate is about 1 Mhz. with oscilloscope i found that signals from ss pin and clk pin falls at the same time(less than 1ns) when a new transfer is started.

 

the system clock is 166Mhz, which means a smallest period is about 6 ns if there's really a delay between the ss and clk signal. i could not imagine how the signals happened to come together within 1 ns after going through fabric and iob.

 

 

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vooalals
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zynq_spips.png

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vooalals
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20,192 Views
Registered: ‎09-30-2014

 

xra1405(the slave) captures input bits[0:n] at rising edges and primes output bits[1:n] at falling edges. i think it is not innocent with this issue because it should only response to falling edges after the first rising edge.

 

you are right, there's no standard document.
thanks a lot for your help.

View solution in original post

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trenz-al
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Registered: ‎11-09-2013

did you reply to my response I deleted? ;)

 

most host should and do keep SS steady during CLK edges. This is used to autodetect SPI mode by the slaves. So Zynq could be more SPI friendly.

 

There are somewhat similat gotchas with zynq I2C too :(

vooalals
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Registered: ‎09-30-2014

yes, i did.

 

finally i removed the pull-up resistor at clk pin so its level is low when idle to avoid this unstability.

implementing a PL spi controller is another solution because zynq is all programmable. :)

 

thanks for your help again.

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