09-02-2014 10:39 AM
i am searching how to get the current value on ZYNQ.
i found this topic
if we talk about estimation using Vivado, what interval can we define it for our real design fonctionnality ?
all report generated by vivado after synthesis step, can we use it to make our real
09-02-2014 02:46 PM
09-02-2014 10:13 PM
Unlike ASIC in FPGA (Including Zynq) everything (IP cores, logic, IO standard, drive strength etc all) is programmable. So we are not able to publishing power consumption directly in our documents since it is mostly dependent on user design (Code).
See the Power Solutions page for power estimation guidelines and tools: