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Anonymous
Not applicable
14,860 Views

[common 17-180] spawn failed: no error

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I am trying to develop a simple UART module. Transmitter and Receiver parts are worked seperately. However, when I try to test both of them in a top module I get " [common 17-180] spawn failed: no error " error firstly and [USF-XSim-62], [Vivado 12-4473] [common 17-39] in sequence.

 

What kind of mistake can cause this error ?

1 Solution

Accepted Solutions
Contributor
Contributor
9,967 Views
Registered: ‎06-06-2019

I think I have found a probable reason for this. I now have 2 versions of the exact same project where one works and the other has this error in Vivado 2018.3. In the Messages, I found another info:

[ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/xxx(removed by me for privacy)'

I think some files are generated with path lengths which are not supported by the OS. I copied the project directly to C:/project_dir and now the same project works fine.

 

View solution in original post

7 Replies
Moderator
Moderator
16,276 Views
Registered: ‎11-09-2015

HI @Anonymous,

 

Could you share a test case? Or at least the vivado.log file showing the issue?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Anonymous
Not applicable
14,759 Views
The problem is solved when I reopened the project. I could not understand what the problem was. However, I guess it was not so critical.
Moderator
Moderator
14,757 Views
Registered: ‎11-09-2015

Hi @Anonymous,

 

Could you mark the issue as solved (mark a post as solution) as you cannot see the issue anymore.

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor
Visitor
12,132 Views
Registered: ‎06-20-2018

I had the same problem, I reopened the project but the problem persists. 

So, this issue is not solved.

This problem should not appear, the message is ambiguous, an error showing "no error" ?!?!? 

Vivado didn´t created a sources folder, so I am not able to copy the files directly to the new project.

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9,992 Views
Registered: ‎02-18-2019

Hi,

I have the same problem. Did you find a solution?  I've also try to close and reopen the project, but the error is still there. Thank you in advance!

 

Regards

Contributor
Contributor
9,968 Views
Registered: ‎06-06-2019

I think I have found a probable reason for this. I now have 2 versions of the exact same project where one works and the other has this error in Vivado 2018.3. In the Messages, I found another info:

[ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/xxx(removed by me for privacy)'

I think some files are generated with path lengths which are not supported by the OS. I copied the project directly to C:/project_dir and now the same project works fine.

 

View solution in original post

Visitor
Visitor
1,479 Views
Registered: ‎05-18-2020

The same error popped up in my case. I had two windows opened, one for the editor and one for the simulation.

I changed the VHDL code and reran the simulation and the [common 17-180] error was displayed in the message window of the simulation window. Turned out I had an actual error in my VHDL code in the editor window but apparently it may take several dozens of seconds before the other window running the simulation and showing [common 17-180] also notices the exact reason for the error caused by code of the other window.

So if you have more than one Vivado window opened, check if you don't have any other errors or wait a couple of seconds before running synthesis/simulation/implementation.

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