11-05-2014 01:38 AM
The design is based on zynq without DDR or FIXED IO PORTS.
and I want the software to run on OCM(on chip memory) of zynq.instead of DDR.
However, I got the critical warnings. such as
"[Netlist 29-160] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. .../sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":30]"
It seems related to constraint file "design_1_processing_system7_0_0.xdc"
If I ignore the critical warnings, DRC error will pop out when running bitstream generate step.
Could somebody help me to work around this issue?
Thanks in advance.
11-05-2014 09:43 PM
11-05-2014 10:27 PM - edited 11-05-2014 10:30 PM
actually I was able to start a new block diagram, add zynq to it and go all the way through the bitmap generation without ddr attached. I think once you do automation, the xdc file is created and you are stuck with it. Try not doing the automation on zynq. ie when you do the automation, unselect the ps/zynq component.
11-09-2014 11:58 PM
Thanks for what you have done.
I tried not to run block automation from the very beginning, but it still pops out the critical warnings about the .xdc.
Actually,before I post the questions, I came across some cases where bitstream could be generated without error.
The problem seems like this. in "smaller" projects which may contain fewer PL other than PS, the bitstream generations seems smooth.
However, in "larger" projects, the btistream will encounter error due to those critical warnings..
I wondered why?