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Registered: ‎06-08-2016

cyclic BD interrupts

I am trying to set up an AXI DMA fed by a Stream FIFO in cyclic SG mode and have some questions as early attempts to get this working are evading me.


I have a Zynq system set up with custom IP feeding data to a Stream Fifo in Packet mode. My custom IP periodically strobes TLAST for one Stream clock cycle. I have the DMA core configured for SG, non-Micro, RX only.


I have SW set up in XSDK with a simple application leveraged from the sg interrupt example. I get one interrupt, I see the data transferred correctly for 1 packet and then nothing. The ring is set up using the example configuration for packet length, interrupt coalesce, number of packets and bds per packet. 

I have ILA in the design and I see the s2mm_introut assert and my ISR fires, shortly thereafter the IRQ deasserts correctly and reasserts again but the second assertion does not result in my ISR firing. 

I have checked the S2MM_STS register all is well - no errors, not halted not idle.


What I really need to be able to do is set up for 2 large buffers in cyclic mode - i.e. set up and start, DMA runs forever ping-ponging between the 2 buffers and interrupting at each buffer completion. It seems like this should be possible. I'm guessing my problem is not completely understanding how to make a buffer transaction complete cause an interrupt on each buffer completion or possibly do interrupts need to be reenabled after each ISR?


Is there an example project somewhere that I can use a s reference to get this unblocked for me?


Any help/advice appreciated ---


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Community Manager
Community Manager
Registered: ‎07-23-2012

We don't have an example design for this. But you can refer to for some guidance.
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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