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deepamj
Adventurer
Adventurer
3,943 Views
Registered: ‎08-19-2009

data transfer delay in PLB

i've connected a vhdl design as peripheral to the microblaze using plb in edk.
microblaze writes data to the peripheral through 21 software registers.
this writing alone takes ~350 cycles.

 

why the data transfer is so much delayed? or is this normal for plb?

how many cycles does PLB  take for  single write or read operation?

Deepa
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3 Replies
dylan
Xilinx Employee
Xilinx Employee
3,940 Views
Registered: ‎07-30-2007

Yes, that could be correct. 350/21 is about 17 cycles per register, especially if the instruction cache is not enabled.  I thought access to a BRAM on the PLB was about 6 cycles, so that plus an instruction fetch would be about right.

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pavithra
Adventurer
Adventurer
3,872 Views
Registered: ‎10-25-2009

hi how to know how many no of clock cycles taking by register operations

thank u

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deepamj
Adventurer
Adventurer
3,484 Views
Registered: ‎08-19-2009

hi

 

added a timer to find the no of cylces

Deepa
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