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Visitor
Visitor
2,259 Views
Registered: ‎09-17-2009

displaying a video from a vga video input

When I want to generate the bitstream, I found this error. 

 

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13>" and IODELAY
   component
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into
   the same I/O tile in order to route net
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/dq_in". The following issue has been detected: 
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56
   where we must place IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement
   requirements of this logic.  IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which
   makes this design unplaceable.  
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/vga_kit_routed] Error 1

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13>" and IODELAY   component   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into   the same I/O tile in order to route net   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g   en_dq[13].u_iob_dq/dq_in". The following issue has been detected:    Some of the logic associated with this structure is locked. This should cause   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56   where we must place IODELAY   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement   requirements of this logic.  IODELAY   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which   makes this design unplaceable.  ERROR:Pack:1654 - The timing-driven placement phase encountered an error.ERROR:Xflow - Program map returned error code 2. Aborting flow execution...make: *** [__xps/vga_kit_routed] Error 1

 

Thanks for help

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1 Reply
Instructor
Instructor
2,257 Views
Registered: ‎07-21-2009

Not enough information.

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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