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Adventurer
Adventurer
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Registered: ‎09-19-2016

dma mm2s : IOC set without transfer being completed

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Using Axi Dma 7.1 (simple mode, 1 mm2s channel) in Vivado 2016.2.

 

I am trying to send only few bytes from PS to custom IP core in PL. In my IP I don't assert tready signal at all (just for debugging purposes), therefore dma start sending first 32-bits of data, but it never sends anything else, which is expected, since tready signal is not asserted. Therefore, tlast is never asserted as well. This is confusing part, since I am getting dma interrupt and IOC flag is set in dma status reg. IOC should be set only when entire transfer is completed isn't that right (when last data is sent)? Why I am getting interrupt then? No sense to me at all.

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Adventurer
Adventurer
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Registered: ‎09-19-2016

 

Now I have noticed that dma hangs when sending more than 516 bytes. Whenever the transfer size is less than this value, the interrupt occurs with IOC set. It seems like dma generates IOC based on whether its own internal output buffer is full or not, and not based on whether the data has been actually sent on the axi stream bus. Correct me if I wrong.

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Adventurer
Adventurer
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Registered: ‎09-19-2016

 

Now I have noticed that dma hangs when sending more than 516 bytes. Whenever the transfer size is less than this value, the interrupt occurs with IOC set. It seems like dma generates IOC based on whether its own internal output buffer is full or not, and not based on whether the data has been actually sent on the axi stream bus. Correct me if I wrong.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Can you probe the AXI MM interface with ILA and post a screenshot?

I think you're right... the DMA probably is issuing an IRQ when it gets rresp back from the memory controller. Thus if your transfer is small enough such that a single burst fits in the internal FIFO buffer, then this behavior will happen.

At first glance, it does seem weird. But really, the point of the IRQ is to tell the software when it can go and set up the next transfer or otherwise do something. Technically, if there's still data in the buffer indefinitely but the commands are all done, the software can go and kick off the next transfer and the DMA will throttle back on the MM interface via rready when that buffer does fill up.

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Adventurer
Adventurer
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Registered: ‎09-19-2016

It seems that is the way DMA works. Here is a screenshot of MM AXI interface before the interrupt signal occurs.

 

mm_axi_interface.PNG

 

In this case I was sending 256 bytes. Integer values I am sending are 1, 2, 3...64. As you can see interrupt occurs after 256 bytes are transferred to DMA, even though ready signal on stream interface is 0 all the time. 

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Visitor
Visitor
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Registered: ‎10-18-2017

Hi x_irie,

Did you find out the solution of this problem? Ist ist a problem in the driver, dma setup or PL?

Regards

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