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Participant
Participant
833 Views
Registered: ‎09-07-2017

errors at dram test

There are  2GB DDR4 in my board, we test memory with SDK Dram Test application.when test a large data write/read.there will be same errors. what should we do? tks a lots

log as follows:

 

*************************************************************************

Starting Memory Test '6' - Testing 1GB length from address 0x0...
---------+--------+------------------------------------------------+-----------
TEST | ERROR | PER-BYTE-LANE ERROR COUNT | TIME
| COUNT | LANES [ #0, #1, #2, #3, #4, #5, #6, #7] | (sec)
---------+--------+------------------------------------------------+-----------
MT0(1: 0)| 8 | 8, 8, 0, 0, 8, 8, 0, 0 | 21.4468
---------+--------+------------------------------------------------+-----------
MTS(1: 1)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.709
---------+--------+------------------------------------------------+-----------
MTS(1: 2)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7097
---------+--------+------------------------------------------------+-----------
MTS(1: 3)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7103
---------+--------+------------------------------------------------+-----------
MTS(1: 4)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7103
---------+--------+------------------------------------------------+-----------
MTS(1: 5)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7103
---------+--------+------------------------------------------------+-----------
MTS(1: 6)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7103
---------+--------+------------------------------------------------+-----------
MTS(1: 7)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7097
---------+--------+------------------------------------------------+-----------
MTS(1: 8)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 10.7103
---------+--------+------------------------------------------------+-----------
MTP(1: 9)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 17.296
---------+--------+------------------------------------------------+-----------
MTP(1:10)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 17.3026
---------+--------+------------------------------------------------+-----------
MTL(1:11)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 18.6383
---------+--------+------------------------------------------------+-----------
MTL(1:12)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 18.6383
---------+--------+------------------------------------------------+-----------
MTL(1:13)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 18.6383
---------+--------+------------------------------------------------+-----------
MTL(1:14)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 18.6383
---------+--------+------------------------------------------------+-----------
Bus Width = 32, D-cache is enable, Verbose Mode is OFF

Enter 'h' to print help menu
Enter Test Option:
7
Starting Memory Test '7' - Testing 2GB length from address 0x0...
---------+--------+------------------------------------------------+-----------
TEST | ERROR | PER-BYTE-LANE ERROR COUNT | TIME
| COUNT | LANES [ #0, #1, #2, #3, #4, #5, #6, #7] | (sec)
---------+--------+------------------------------------------------+-----------
MT0(1: 0)| 40 | 40, 40, 0, 0, 37, 40, 0, 0 | 42.8924
---------+--------+------------------------------------------------+-----------
MTS(1: 1)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 21.4173
---------+--------+------------------------------------------------+-----------
MTS(1: 2)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 21.418
---------+--------+------------------------------------------------+-----------
MTS(1: 3)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 21.4187
---------+--------+------------------------------------------------+-----------
MTS(1: 4)| 8 | 8, 8, 0, 0, 8, 8, 0, 0 | 21.418
---------+--------+------------------------------------------------+-----------
MTS(1: 5)| 16 | 16, 16, 0, 0, 16, 16, 0, 0 | 21.5923
---------+--------+------------------------------------------------+-----------
MTS(1: 6)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 21.418
---------+--------+------------------------------------------------+-----------
MTS(1: 7)| 72 | 72, 72, 0, 0, 72, 72, 0, 0 | 21.401
---------+--------+------------------------------------------------+-----------
MTS(1: 8)| 16 | 16, 16, 0, 0, 16, 16, 0, 0 | 21.401
---------+--------+------------------------------------------------+-----------
MTP(1: 9)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 34.5907
---------+--------+------------------------------------------------+-----------
MTP(1:10)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 34.5907
---------+--------+------------------------------------------------+-----------
MTL(1:11)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 37.2754
---------+--------+------------------------------------------------+-----------
MTL(1:12)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 37.2754
---------+--------+------------------------------------------------+-----------
MTL(1:13)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 37.2754
---------+--------+------------------------------------------------+-----------
MTL(1:14)| 0 | 0, 0, 0, 0, 0, 0, 0, 0 | 37.2754
---------+--------+------------------------------------------------+-----------
Bus Width = 32, D-cache is enable, Verbose Mode is OFF

Enter 'h' to print help menu
Enter Test Option:

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2 Replies
Highlighted
Advisor
Advisor
809 Views
Registered: ‎04-26-2015

Re: errors at dram test

@zebulon I'd have a look at both the MIG/PS settings for the four byte lanes that are causing problems, and also the PCB layout for those lanes. For example, are there four chips, each with two byte lanes? If so, is it possible that two chips were soldered incorrectly? Or are those two byte lanes routed in a less-than-optimal way that might be introducing noise?

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Participant
Participant
804 Views
Registered: ‎09-07-2017

Re: errors at dram test

@u4223374

Thanks for your reply!

we use two chips,each with four byte lanes.as ds925 table30. xczu2eg-SV484 DDR controller just run 1066Mbps,we set the DDR clk as 533MHz in vivado,same boad will failed. but we set clk as 500MHz, all board are successed.

 

 

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