cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
yang0
Visitor
Visitor
380 Views
Registered: ‎03-31-2020

fifo+dma+ddr problem

I have a system that transfer 256bits data width steam data to 512bits ddr4, and steam data assert tlast every 16*256bits.

axi dma configuration as follow,direct mode, interrupt , setting length enough.but work badly.

one problem is s2mm interrupt asserted interval when transfer 16*256,1*256,16*256,1*256 data.expectly all is 16*256. 

another is ddr data , lower 256bits ok. but higher 256bits filled with last 256bits data.

Any suggestion? thanks.

dma.bmp
0 Kudos
1 Reply
yang0
Visitor
Visitor
348 Views
Registered: ‎03-31-2020

add 2 pic to show the problem

ila_0.bmp
ila_ddr.png
0 Kudos