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Adventurer
Adventurer
4,689 Views
Registered: ‎01-14-2014

fsync_in & fsync_out[n : 0] in Video timing Controller IP

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Hi,

I am facing problem in driving fsync in signal in VTC ip.

what signal from Video in to axi out ip will drive this signal and what this signal signify.

and same how to utilize fsync_out and why it has some width.

what is it signify.

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Xilinx Employee
Xilinx Employee
6,044 Views
Registered: ‎07-11-2011

Hi,

 

Assuming high period of fsync_out  signifies frame start, its hight time can be used as synchronization signal to susequent modules.

For the display device it has some internal functions like the raster has to trace back from right bottom pixel to left top pixel.

Assume it as a reset with some pulse width.

 

det_aclken and gen_aclken are inputs to VTC,  they are  clock enables for detector and geneator clocks.

You can drive them externally or can tie them to logic high always. 

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
4,687 Views
Registered: ‎07-11-2011

Hi,

 

Fsync signifies frame start.

It has some width based on your configuration, however you will not receive any data in its deactive period.

Note that fsync has polarity as well, please do google search for frame start signal details.

PG043  figure 3-5 will show you teh connectivity of VTC , AXI blocks

 

http://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v3_0/pg043_v_vid_in_axi4s.pdf

 

 

Regards,

Vanitha.

 

 

 

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Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Xilinx Employee
Xilinx Employee
4,682 Views
Registered: ‎07-11-2011

Hi,

 

If you are new to Video designs i would suggest you to go through UGs in teh below link and pick one of the reference design so that it gives you a good start.

 

http://www.xilinx.com/esp/video/refdes_listing.htm

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Adventurer
Adventurer
4,679 Views
Registered: ‎01-14-2014

 

Thanks for your valuable support.Please clear some more doubts about these signals

 

And one more doubt in this.

why fsync_out if i say it show frame start for axi4in to video out ip, then what its width signifies.

i searched it about this but i didnt got solution for this,

and det_aclken and gen_aclken are dependent on other signals or must be provided externally, and how to control these enable signals .

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Adventurer
Adventurer
4,676 Views
Registered: ‎01-14-2014

yes i am also seeing these ugs.

but some doubts being arise and making problem in design, doubts may be silly.

but thanks for your support.

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Xilinx Employee
Xilinx Employee
6,045 Views
Registered: ‎07-11-2011

Hi,

 

Assuming high period of fsync_out  signifies frame start, its hight time can be used as synchronization signal to susequent modules.

For the display device it has some internal functions like the raster has to trace back from right bottom pixel to left top pixel.

Assume it as a reset with some pulse width.

 

det_aclken and gen_aclken are inputs to VTC,  they are  clock enables for detector and geneator clocks.

You can drive them externally or can tie them to logic high always. 

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post