09-22-2013 11:48 PM
Hi, i have a design with axi stream interface, and in order to integrate using IPI(Vivado 2013.2), i have to pack this IP first.
and the FREQ_HZ parameter must be pre-defined(ex. 50MHz).
However, the actural system freq could vary and adjust in other zynq project, if the system clk is different from the pre-defined value, error occurs.
if this FREQ_HZ become global parameter, and can be adjusted after packaging with IPI GUI, the entire design flow
would be better and less iteration.
is this possible?
09-06-2016 04:02 PM
I have the same problem.
It would be very useful to be able to
1. define input parameters for the block design module of a project
2. use these parameters for the values of FREQ_HZ in blocks or to pass to submodules
09-09-2016 05:30 AM
09-09-2016 01:23 PM
please don't post to 2 year old threads. Create a new thread.
Even if it's related and helps to keep all relevant responses in the same post? Isn't that more preferable? Sorry if this isn't the accepted approach, but I'm genuinely interested as to why it's better to have a topic scattered over several threads instead of in one?
03-27-2019 08:59 AM - edited 03-27-2019 09:11 AM
Apologies for adding a response to a very old thread but I had a similar issue and could not find a solution anywhere.
I am posting here in case anyone else comes across this and needs a painful but effective solution that can be implemented without resorting to manual methods per http://www.xilinx.com/support/answers/56610.htm.
For a situation with many clocks it is tedious to manually apply FREQ_HZ parameters in the IP Packager GUI. Whenever a change is made to the source design, it is obnoxious to have to repeatedly do many manual edits in the IP Packager GUI.
It is possible to use TCL and file editing - with SED or equivalent - to eliminate the need for manual GUI actions.
For my custom IP, generated from a block design and the IP packager, I used IPX TCL console commands similar to this to add the FREQ_HZ parameter to my clocks. In my case I had 16 clocks with names of a form [M|S]_[R|T]X[0-7]_ACLK.
ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces M_TX0_ACLK -of_objects [ipx::current_core]]
After completing package IP the component.xml file can then be edited to add the FREQ_HZ value.
To this (in my case 156.25Mhz was the desired value):
Re-editing with the IP Packager will verify that the FREQ_HZ values have been added. Updating the IP in the parent block design and re-running Validate Design will verify elimination of mismatched frequency settings.
I am sure there must be a better way but I couldn't figure one out and at least this allows me to use command line methods rather than manual GUI actions to add and set the FREQ_HZ parameter to my custom IP's clocks.
05-21-2019 07:02 AM - edited 05-21-2019 07:03 AM
It is actually possible. Here are the tcl commands:
ipx::infer_bus_interface clk_125 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces clk_125 -of_objects [ipx::current_core]] set_property value 125000000 [ipx::get_bus_parameters FREQ_HZ -of_objects [ipx::get_bus_interfaces clk_125 -of_objects [ipx::current_core]]]