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zhangjun_beijing
Participant
Participant
762 Views
Registered: ‎05-27-2016

how will the address increase when use narrow size to write data to PS ddr3 through s_axi_hp interface?

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how will the address increase when use narrow size to write data to PS ddr3 through s_axi_hp interface?

I use zynq bfm ip to simulate s_axi_hp interface.

s_axi_hp is 64 bits size. I set awsize is "001",  means 16 bits size. I write data to ps side ddr3, then read back. I found awsize is not valid, 64 bits size is only useful.

I want to know whether zynq s_axi_hp bus support narrow size mode? 

 

thanks

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savula
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Moderator
633 Views
Registered: ‎10-30-2017

Hi @zhangjun_beijing ,

 

Yes, the narrow burst on S_AXI_HP port is suuported. please check whether it is enabled or not in your design:

image.png

 

Best Regards,
Srikanth
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savula
Moderator
Moderator
634 Views
Registered: ‎10-30-2017

Hi @zhangjun_beijing ,

 

Yes, the narrow burst on S_AXI_HP port is suuported. please check whether it is enabled or not in your design:

image.png

 

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
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zhangjun_beijing
Participant
Participant
583 Views
Registered: ‎05-27-2016

hi,

I use zynq_processing_system_bfm ip to simulate. This ip have not this config option. I don't know if zynq_processing_system ip can simulate. I will try.

 

thanks.

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savula
Moderator
Moderator
513 Views
Registered: ‎10-30-2017

Hi @zhangjun_beijing ,

 

I am able to see the narrow burst support for Zynq also. please check below image:

image.png

Best Regards,
Srikanth
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