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Explorer
Explorer
7,216 Views
Registered: ‎11-16-2012

issue in writing data to the Block RAM ?

I have a design in which my block ram Gen is connected to Bram controller and one controller is accessible through my custom ip  although another controller is connected to zynq processor. 

 

I have strange probelm ! I can read the memory content of BRAM but I cannot write to it !! I see no error message also... 

 

Thanking you very much!!

 

Regards

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Scholar
Scholar
7,201 Views
Registered: ‎02-27-2008

v,

 

Perhaps you could post a copy of the ip blocks which shows how they are connected?

 

http://www.xilinx.com/products/design-tools/vivado/integration.html

 

There are too many variable here to just guess why you have the problem,

Austin Lesea
Principal Engineer
Xilinx San Jose
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Newbie
Newbie
7,191 Views
Registered: ‎01-15-2015

Hi,

 

I was having the same error. It was only a stupid bug from myself : bad polarity of reset.

so , you can check reset polarity (1 active wheras 0 active for arm) and also the write enable

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Explorer
Explorer
7,182 Views
Registered: ‎11-16-2012

image_1.png

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Explorer
Explorer
7,177 Views
Registered: ‎11-16-2012

I would be glad if you check this issue! as this issue is reproducible (in my case at least !)....but it happens only if you try to make a bd subsystem (which has bram as shown in diagram). and import it in another project .

 

I would also like to point that I have receive this criticalwarning!

 

[Memdata 28-122] data2mem failed with parsing error. check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components  initialization strings have not been updated.

 

for this i followed the following post

 

http://www.xilinx.com/support/answers/59639.html

 

I am using vivado 2014.4

 

many thanks for help!

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Explorer
Explorer
7,175 Views
Registered: ‎11-16-2012

Thanks for your reply. But this is not the reason in my case unfortunately !!

 

Regards

 

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Scholar
Scholar
7,174 Views
Registered: ‎02-27-2008

looks like everything is there,


And connected properly.  I see two BRAM controllers, one for A and another for B port.  I suggest you create  a design with ChipScope ILA and probe the A and B ports of the BRAM, so you can "see" the reads and writes to debug.

 

Check the addressing of the A and B ports, and check that you have both read and write capabilities enabled in the AXI interfaces.  TrustZone(ARM tm) is implemented on AXI interfaces, so be sure you either declare it unused, or you are using it properly (as that will interfere with use if not in agreement).

 

The debug program you use should be as simple as posible, until you have the hardware working. (Not much more than a "Hello World" to read some data, and write some data...0.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
7,146 Views
Registered: ‎11-16-2012

@austin 

 

Many thanks for your message!

 

This issue arise when I to configure my custom_ip master interface with datawidth 128. Everything works fine as long as i works with 64 bits. 

 

I receive this error ..

CRITICAL WARNING: [Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.

 

Could you help me in understanding my mistake here...

 

Thank you very much!

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