cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
314 Views
Registered: ‎04-30-2019

issue with RTC Block Diagram on Zynq Ultrascale+ documentation (fig 7-2 in UG1085 V1.9)

It is my first post here, so I hope it lands in the right place.

I am reading through UG1085 V1.9. On page 163 I am puzzeled by the RTC controller Functional Block Diagram. In particular with the wiring of the CALIB_WRITE[Fraction_En] signal. I have highlighted it in the picutre below. In my understanding, feeding the inverse of that signal to the triple AND gate in the middle of the diagram means that when CALIB_WRITE[Fraction_En] is high, the Seconds Counter is not incremented anymore. I don't see this being desirable.Or did I miss something?

 

xilinxug1085.PNG

0 Kudos
0 Replies