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dosim
Visitor
Visitor
8,148 Views
Registered: ‎10-10-2008

level vs. edge sensitive interrupt control

Hi All

 

I am using an EDK project on Xilinx Spartan 3E 1600.  We have 4 interrupts into a interrupt controller and the output of the interrupt controller is wired into our MicroBlaze processor.

 

The issue is this: we cannot change the character on the output of the interrupt controller.  The output of the interrupt controller is always edge sensitive acting on rising edge.  We would like the output of the interrupt controller to be level sensitive active on level high.  This change is desired because the input to the MicroBlaze interrupt is set at level senstive acting on level high, and we need to match the senstivity of the output of the interrupt controller to the input of the microblaze since they are wired together.  All 4 inputs to the interrupt controller are edge sensitive acting on rising edge.

 

If anyone knows how to change the character of the output of the interrupt controller from edge-rising to level-high please let me know.

 

Thanks very much for your time.

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4 Replies
flitch@mbda
Contributor
Contributor
8,135 Views
Registered: ‎06-22-2009

Hi,

 

If you are using the Xilinx IP (xps_intc) for the interrupt controller then double click on the instance name in your EDK design. This will pop up a dialog box. One of the drop down options is output interrupt polarity. Basically high/rising or low/falling are the only two options.

 

However, if you want to change the polarity of the input to this block (i.e. from your IP). Then you can modify the .mpd file for the IP. This will contain a definition of the interrupt pin with the SENSITIVITY = LEVEL_HIGH statement. I presume you can change this to get another polarity.

 

I have never actually done this, so good luck.

 

Best wishes

Peter

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dosim
Visitor
Visitor
8,125 Views
Registered: ‎10-10-2008

Thanks Peter

 

We've tried that and it does not seam to help.  The attribute of the output signal is still labeled as Edge/Rising.  In either case, it would not change it from an edge sensitive into a level sensitive signal.  We are using the interrupt IP from Xilinx and the microblaze IP from Xilinx, its actually kind of surprising that they don't match.

 

Any thoughts would be welcomed.

 

Thanks for your time.

 

Meng

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jagron
Adventurer
Adventurer
8,122 Views
Registered: ‎01-04-2008

The XPS interrupt controller (xps_intc) has an interrupt output ("interrupt" IRQ output port) that is level sensitive (active high or low).  However, the inputs to the interrupt controller can be configured to be edge sensitive.  This output stays asserted until a processor acknowledges all pending interrupts.

 

XPS INTC Guide:

 

"Output interrupt request pin is configurable for level generation - active high or active low"

 

-Jason

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htsvn
Xilinx Employee
Xilinx Employee
8,083 Views
Registered: ‎08-02-2007

 Hi,

 

Check this

 

http://www.xilinx.com/support/answers/32608.htm

 

Thanks.

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