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doner_t
Explorer
Explorer
5,931 Views
Registered: ‎04-19-2016

low datarate has been read from DDR3 of Xc7Z020 processors

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Hello,

 

We have measured the Bandwidth of the DDR3, via basic write-read test, that is connected to the PS side of Zynq XC7Z020. 

DDR3 specs are 32- bit, 533 MHz. But BW results are seen nearly 120 MB/s . It is too low...Why is this BW seen so low ?

There are also another DDR3 bank that is connected to the PL side of XC7Z020 . But how can I write PS side DDR3 from the PL side ? 

 

Best regards,

TD

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vsrunga
Xilinx Employee
Xilinx Employee
10,917 Views
Registered: ‎07-11-2011

@doner_t

 

For Q1, Performance depends on many factors like your address pattern, memory timing parameters, refresh etc.,

You can run a simulation with your address pattern and calculate the effective bandwidth and determine the actual overhead that the controller is imposing.

 

For Q2, below links may help you 

http://www.xilinx.com/support/answers/53320.html

http://zedboard.org/content/how-access-data-ddr-ps-side-pl-part

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/PL-DDR-in-ZC706/td-p/331397

 

-Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
10,918 Views
Registered: ‎07-11-2011

@doner_t

 

For Q1, Performance depends on many factors like your address pattern, memory timing parameters, refresh etc.,

You can run a simulation with your address pattern and calculate the effective bandwidth and determine the actual overhead that the controller is imposing.

 

For Q2, below links may help you 

http://www.xilinx.com/support/answers/53320.html

http://zedboard.org/content/how-access-data-ddr-ps-side-pl-part

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/PL-DDR-in-ZC706/td-p/331397

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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