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Observer
Observer
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Registered: ‎04-23-2019

lwip axidma_recv_handler

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Hi there,

I have issues with the LwIP running on Microblaze on VC707 board.

I've tried to use the BIST reference design that is already embedding the ethernet modules. As it was designed for earlier vivado release, there are some IP upgrades to perform. Bitstream is then generated as expected.

Then i'm implementing the echo server from the Vitis example. I do not import the SDK projects from the reference design, but i'm generating the echo server example only.

Vivado 2019.2  / Vitis  2019.2 64bits / LwIP 211_v1_1

I've tried to specify the linker memory options to use the same configuration as specified in the previous SDK project (all memory in BRAM), and also by using the mig_memory (DDR) but it doesn't help.

At first everything is running smoothly, i can echo the transmitted data back to my putty terminal. But after a short time (not determinisitic, could be 1, or 10 minutes...) i received the following error:

axidma_recv_handler : Error: axidma error interrupt is asserted

and most of the time, the FPGA is frozen.

Tracing back the piece of code that is printing this message, i found that it comes from the file \microblaze_0\standalone_domain\bsp\microblaze_0\libsrc\lwip211_v1_1\src\contrib\ports\xilinx\netif\xaxiemacif_dma.c 

i don't think i need to update this part of the code as it is widely used and should not have issue. I'm wondering why i'm having this error and how to deal with it?

Do i need to intercept it and handle it in a different way? Doesn't seem wise.. 

Reading old forum posts seems i do not find answers as they are more related to old piece of software that have been updated since then. 

If someone as an idea on where to dig, feel free! 

thank you!

https://forums.xilinx.com/t5/Ethernet/LwIP-VC707-Echo-problem/m-p/712886#M9648

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Microblaze-Lwip-dma-handle-error/m-p/823302#M21664

https://forums.xilinx.com/t5/Embedded-Development-Tools/LWIP-RX-interrupt-corrupts-register/m-p/548459#M33786

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/get-axidma-recv-handler-Error-axidma-error-interrupt-is-asserted/m-p/986431#M46122

https://forums.xilinx.com/t5/Ethernet/Error-axidma-error-interrupt-is-asserted/td-p/836044

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/XAPP1026-without-DDR/td-p/473902

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Observer
Observer
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Registered: ‎04-23-2019

Hi there, finally i've downloaded the previous vivado release (2019.1), and I don't see the error anymore. It must be a bug somewhere in the latest version or in the ip updates...

So many weeks spent for that... Anyway I can carry on now.

View solution in original post

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Observer
Observer
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Registered: ‎04-23-2019

Hi there,

i'm still stuck with this issue. it makes a few weeks now that i'm trying a lot of things without any success.

i've tested the BIST reference design made on vivado 2015.1 and updated it vivado 2019.2 with lwip 2.1.1 -> error

I've also tested the  NoBRAMPowerOpt set in Vivado -> error  https://forums.xilinx.com/t5/Xilinx-IP-Catalog/BRAM-connections-change-in-implementation/m-p/729630

without any difference. After a while, the axidma_recv_handler is asserted and cannot resume from this state. I've try to comment/update the error of the handler but no luck as weel. Error returned in irq_status is 0x5000 but i was not able to debug further as there were no symbols attached.

I've downloaded vivado 2015.1 and recompile the reference design: everything is working. i have not seen the issue... from this Block design, i've created the same one and take care of the parameters in 2019.2 but error was still there.

I've updated heap/stack size to big values (more than 1MB), change the memory location.. 

 

For few minutes everything is workign smoothly, but after a (short) while, the assertion occurs..

I've tried to change the link speed to 10 or 100 Mbps, but it must requires different settings as the link goes up/down forever.

vc707_lwip_error.png

Any help is welcome

Thank you, 

 

V.

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Highlighted
Observer
Observer
151 Views
Registered: ‎04-23-2019

Hi there, finally i've downloaded the previous vivado release (2019.1), and I don't see the error anymore. It must be a bug somewhere in the latest version or in the ip updates...

So many weeks spent for that... Anyway I can carry on now.

View solution in original post

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