cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
437 Views
Registered: ‎08-22-2019

package IP

hi everyone this is my first time posting here and need some help.
 
I am using the Real Digital blackboard with Zynq chip and have created a verilog file that is basically a pulse generator with variable pulse width. This pulse width is selected by users.
 
What I want is to have a terminal (using embedded ARM core) where user can input pulse width desired (only a few discrete pulse widths) and transfer this input into my fpga hardware where I can output pulse on one of the gpio pins. 
 
Here is what I have done so far:
  • I have successfully created and tested the verilog file and tested using onboard switches as inputs.
  • I then created axi4 IP with my code instantiated in it. I saw a tutorial online to do this. However, I want the my fpga hardware to operate on the fpga clk (100MHz) not on the slow axi clock. So when I instantiate I am not sure what to do with the output signal and clk signal. I tried adding a constraint file for the output and clk but I dont think this works. 
  • I then generate my ip and connect it in block diagram to zync....
  • I then export....and open SDK but obviously it doesnt run when I launch. This I am certain is due to the output signal and clk signal not routed properly but I do not know what to do about them.

Any help would be greatly appreciated.

Tags (2)
0 Kudos
1 Reply
katsuki
Xilinx Employee
Xilinx Employee
371 Views
Registered: ‎11-05-2019

 

Hello bperez65020@gmail.com 

You can create a custom IP with AXI I/F, see UG1118 and UG1119.

The connection between the AXI I/F and the internal logic must be built in and depends on the custom IP.

Thank you


Don't forget to reply, kudo, and accept as solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
0 Kudos