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Registered: ‎02-27-2019

pls help to the the sch design for ku115(f1924)

1.Is here a large current when the Ku115 is power up or before the bit files is downloaded ?

2.In my case, I have do the XGE function in the some Quad(the Quads have the serial numbers: bank230~bank232).Can I only use one MGTrefClk(156.25M) into one Quad, and the other Quad use the same reference clk ?

3. I find the GC-CLK have the terminal resistor(100 ohm) in the HP-Bank of the demo board.And all of the lvds signal or clk have no terminal.So, can I remove all of the terminal resistor on the lvds signal/clk and GC-clk?

4. in my case, I do the FMC-HPC function also.But I find the FMC’s CC signal is connected to the GC pin, but not the QBC ? Which one is better ?

5. I don’t need the ddr chips. So I let the VREF pin of all the Bank to float.

6.I connect the GTX’s rx-data to GND, because they are not used in my case.

7.I connect the VCC-IO to GND, when the Bank is not it ok ? my case, I do the mipi function, and I use the meticom’s chip.I connect the HS and LS signals to the HP-Bank, not the GTH.And in the Bank, have the another function signals ,is it ok ?

9. ku115’s Vccaux_io and Mgtavtt have a lot of pins,But I get the current is so small with full speed.

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