problem instantiating Microblaze MCS on coregen: missing system_template.tcl

[aventuri]

hello guys,

this is first time i'm writing on the forum. so be gentle! :-)

first few bits on my status on FPGA: 

i've tried to do all my home work and in the last few months i've paved my way steadily through the basics of the FPGA world. i've a SP605 development kit and i've been able to test some designs on my own, light some led with the buttons, use the diff clock for counters, test the Picoblaze soft proc reading the tutorial with also the UART demo (what a great little IP core that..). so far so good.

now i'd like to test the Microblaze MCS through ISE/coregen (as i've got only ISE Logic Edition)  but i'm stopped on an error during implementation step. the coregen debug log spits out that it doesn't find the "system_template.tcl" anywhere in my local project directory (i see it buried down in the Xilinx ISE tree so it seems someone "forgot" to copy in the right place at the right time..)

see down here the last few lines of the coregen debug log:

....

"/home/andrea/progetti/fpga/designs/mcs-microblaze/test1/ipcore_dir/tmp/_cg/microblaze_mcs_v1_2.ngc" -intstyle xflow'...
DEBUG[tcl_generator] - Finished executing Tcl generator.
DEBUG[tcl_generator] - Executing Sim_TclCommandExecutor::Execute()
DEBUG[designenvironment] - No padded netlist requested.
DEBUG[tcl_generator] - Finished executing Tcl generator.
DEBUG[tcl_generator] - Executing Sim_TclCommandExecutor::Execute()
INFO:sim - Running microblaze_mcs_gen_script.tcl
DEBUG[designenvironment] - C_FAMILY = spartan6
DEBUG[designenvironment] - C_PATH = mcs_0/U0
DEBUG[designenvironment] - C_PATH = mcs_0/U0
DEBUG[designenvironment] - C_XDEVICE = xc6slx45t
DEBUG[designenvironment] - C_XPACKAGE = fgg484
DEBUG[designenvironment] - C_XSPEEDGRADE = -3
DEBUG[designenvironment] - C_MICROBLAZE_INSTANCE = microblaze_mcs_v1_2
DEBUG[designenvironment] - C_FREQ = 100000000
DEBUG[designenvironment] - C_MEMSIZE = 8192
DEBUG[designenvironment] - C_DEBUG_ENABLED = 0
DEBUG[designenvironment] - C_USE_IO_BUS = 0
DEBUG[designenvironment] - C_USE_UART_RX = 1
DEBUG[designenvironment] - C_USE_UART_TX = 1
DEBUG[designenvironment] - C_UART_BAUDRATE = 115200
DEBUG[designenvironment] - C_UART_PROG_BAUDRATE = 0
DEBUG[designenvironment] - C_UART_DATA_BITS = 8
DEBUG[designenvironment] - C_UART_USE_PARITY = 0
DEBUG[designenvironment] - C_UART_ODD_PARITY = 0
DEBUG[designenvironment] - C_UART_RX_INTERRUPT = 0
DEBUG[designenvironment] - C_UART_TX_INTERRUPT = 0
DEBUG[designenvironment] - C_UART_ERROR_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_FIT1 = 0
DEBUG[designenvironment] - C_FIT1_No_CLOCKS = 6216
DEBUG[designenvironment] - C_FIT1_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_FIT2 = 0
DEBUG[designenvironment] - C_FIT2_No_CLOCKS = 6216
DEBUG[designenvironment] - C_FIT2_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_FIT3 = 0
DEBUG[designenvironment] - C_FIT3_No_CLOCKS = 6216
DEBUG[designenvironment] - C_FIT3_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_FIT4 = 0
DEBUG[designenvironment] - C_FIT4_No_CLOCKS = 6216
DEBUG[designenvironment] - C_FIT4_INTERRUPT =0
DEBUG[designenvironment] - C_USE_PIT1 = 0
DEBUG[designenvironment] - C_PIT1_SIZE = 32
DEBUG[designenvironment] - C_PIT1_READABLE = 1
DEBUG[designenvironment] - C_PIT1_PRESCALER = 0
DEBUG[designenvironment] - C_PIT1_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_PIT2 = 0
DEBUG[designenvironment] - C_PIT2_SIZE = 32
DEBUG[designenvironment] - C_PIT2_READABLE = 1
DEBUG[designenvironment] - C_PIT2_PRESCALER = 0
DEBUG[designenvironment] - C_PIT2_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_PIT3 = 0
DEBUG[designenvironment] - C_PIT3_SIZE = 32
DEBUG[designenvironment] - C_PIT3_READABLE = 1
DEBUG[designenvironment] - C_PIT3_PRESCALER = 0
DEBUG[designenvironment] - C_PIT3_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_PIT4 = 0
DEBUG[designenvironment] - C_PIT4_SIZE = 32
DEBUG[designenvironment] - C_PIT4_READABLE = 1
DEBUG[designenvironment] - C_PIT4_PRESCALER = 0
DEBUG[designenvironment] - C_PIT4_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_GPO1 = 1
DEBUG[designenvironment] - C_GPO1_SIZE = 32
DEBUG[designenvironment] - C_GPO1_INIT = 0x00000000
DEBUG[designenvironment] - C_USE_GPO2 = 0
DEBUG[designenvironment] - C_GPO2_SIZE = 32
DEBUG[designenvironment] - C_GPO2_INIT = 0x00000000
DEBUG[designenvironment] - C_USE_GPO3 = 0
DEBUG[designenvironment] - C_GPO3_SIZE = 32
DEBUG[designenvironment] - C_GPO3_INIT = 0x00000000
DEBUG[designenvironment] - C_USE_GPO4 = 0
DEBUG[designenvironment] - C_GPO4_SIZE = 32
DEBUG[designenvironment] - C_GPO4_INIT = 0x00000000
DEBUG[designenvironment] - C_USE_GPI1 = 1
DEBUG[designenvironment] - C_GPI1_SIZE = 32
DEBUG[designenvironment] - C_GPI1_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_GPI2 = 0
DEBUG[designenvironment] - C_GPI2_SIZE = 32
DEBUG[designenvironment] - C_GPI2_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_GPI3 = 0
DEBUG[designenvironment] - C_GPI3_SIZE = 32
DEBUG[designenvironment] - C_GPI3_INTERRUPT = 0
DEBUG[designenvironment] - C_USE_GPI4 = 0
DEBUG[designenvironment] - C_GPI4_SIZE = 32
DEBUG[designenvironment] - C_GPI4_INTERRUPT = 0
DEBUG[designenvironment] - C_INTC_USE_EXT_INTR = 1
DEBUG[designenvironment] - C_INTC_INTR_SIZE = 1
DEBUG[designenvironment] - C_INTC_LEVEL_EDGE = 0x0000
DEBUG[designenvironment] - C_INTC_POSITIVE = 0xFFFF
WARNING:coreutil - no files matched glob pattern "./_cg/*/system_template.tcl"
while executing
"glob "./_cg/*/system_template.tcl""
(procedure "bmm_xml" line 242)
invoked from within
"bmm_xml $argc $argv"
invoked from within
"return [bmm_xml $argc $argv]"
(file
"/opt/Xilinx/14.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/microblaze_mcs_gen_script.tcl" line 479)ERROR:sim - Unable to evaluate Tcl file:
/opt/Xilinx/14.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/microblaze_mcs_gen_script.tcl
ERROR:sim - Failed executing Tcl generator.

===================================================

i've tried to google here and there for such an error but missed to find useful info.

the curious thing is that i happen to get the same error on two different ISE installation, a 14.2 Logic Edition and a 14.1 plain ISE webpack (on a netbook, for exercising when commuting, but slow as hell..)

i'm wondering if i can provide more info about it..

i have the "xsdk" (SDK) installed. i can launch it, but of course it doesn't find the "hardware description" file for this ccore.

BTW the file left in the "ipcore_dir" of my otherwise empty ISE test project are these:

andrea@nb-andrea:~/progetti/fpga/designs/mcs-microblaze/test1/ipcore_dir$ tree
.
├── coregen.cgc
├── coregen.cgp
├── coregen.log
└── tmp
├── _cg
│   ├── microblaze_mcs_v1_2.bmm
│   ├── microblaze_mcs_v1_2_dbg
│   │   ├── axi_lite_ipif_v1_01_a
│   │   │   └── pcores
│   │   │   └── axi_lite_ipif_v1_01_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── address_decoder.vhd
│   │   │   ├── axi_lite_ipif.vhd
│   │   │   └── slave_attachment.vhd
│   │   ├── _default.lso
│   │   ├── iomodule_v1_01_a
│   │   │   └── pcores
│   │   │   └── iomodule_v1_01_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── divide_part.vhd
│   │   │   ├── fit_module.vhd
│   │   │   ├── gpi_module.vhd
│   │   │   ├── gpo_module.vhd
│   │   │   ├── intr_ctrl.vhd
│   │   │   ├── iomodule_core.vhd
│   │   │   ├── iomodule.vhd
│   │   │   ├── pit_module.vhd
│   │   │   ├── pselect_mask.vhd
│   │   │   ├── uart_control_status.vhd
│   │   │   ├── uart_receive.vhd
│   │   │   ├── uart_transmit.vhd
│   │   │   └── xilinx_primitives.vhd
│   │   ├── lmb_bram_if_cntlr_v3_10_a
│   │   │   └── pcores
│   │   │   └── lmb_bram_if_cntlr_v3_10_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── axi_interface.vhd
│   │   │   ├── checkbit_handler.vhd
│   │   │   ├── correct_one_bit.vhd
│   │   │   ├── lmb_bram_if_cntlr.vhd
│   │   │   ├── lmb_bram_if_funcs.vhd
│   │   │   ├── lmb_mux.vhd
│   │   │   ├── parityenable.vhd
│   │   │   ├── parity.vhd
│   │   │   ├── plb_interface.vhd
│   │   │   ├── pselect_mask.vhd
│   │   │   ├── pselect.vhd
│   │   │   └── xor18.vhd
│   │   ├── lmb_v10_v2_00_b
│   │   │   └── pcores
│   │   │   └── lmb_v10_v2_00_b
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   └── lmb_v10.vhd
│   │   ├── mdm_v2_10_a
│   │   │   └── pcores
│   │   │   └── mdm_v2_10_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── jtag_control.vhd
│   │   │   ├── mdm_core.vhd
│   │   │   ├── mdm.vhd
│   │   │   └── srl_fifo.vhd
│   │   ├── microblaze_mcs_v1_2
│   │   │   └── hdl
│   │   │   ├── lmb_bram.vhd
│   │   │   ├── microblaze_mcs.vhd
│   │   │   └── ram_module_top.vhd
│   │   ├── microblaze_mcs_v1_2.log
│   │   ├── microblaze_mcs_v1_2.ngc
│   │   ├── microblaze_mcs_v1_2.ngc_xst.xrpt
│   │   ├── microblaze_mcs_v1_2.prj
│   │   ├── microblaze_mcs_v1_2.scr
│   │   ├── microblaze_mcs_v1_2.vhd
│   │   ├── microblaze_mcs_v1_2.xlpp
│   │   ├── microblaze_mcs_v1_2_xsd
│   │   │   ├── axi_lite_ipif_v1_01_a
│   │   │   │   ├── axi_lite_ipif_v1_01_a.vdbl
│   │   │   │   └── axi_lite_ipif_v1_01_a.vdbx
│   │   │   ├── dump.xst
│   │   │   │   └── microblaze_mcs_v1_2.prj"
│   │   │   ├── iomodule_v1_01_a
│   │   │   │   ├── iomodule_v1_01_a.vdbl
│   │   │   │   └── iomodule_v1_01_a.vdbx
│   │   │   ├── lmb_bram_if_cntlr_v3_10_a
│   │   │   │   ├── lmb_bram_if_cntlr_v3_10_a.vdbl
│   │   │   │   └── lmb_bram_if_cntlr_v3_10_a.vdbx
│   │   │   ├── lmb_v10_v2_00_b
│   │   │   │   ├── lmb_v10_v2_00_b.vdbl
│   │   │   │   └── lmb_v10_v2_00_b.vdbx
│   │   │   ├── mdm_v2_10_a
│   │   │   │   ├── mdm_v2_10_a.vdbl
│   │   │   │   └── mdm_v2_10_a.vdbx
│   │   │   ├── microblaze_mcs_v1_2
│   │   │   │   ├── microblaze_mcs_v1_2.vdbl
│   │   │   │   └── microblaze_mcs_v1_2.vdbx
│   │   │   ├── microblaze_v8_40_a
│   │   │   │   ├── microblaze_v8_40_a.vdbl
│   │   │   │   └── microblaze_v8_40_a.vdbx
│   │   │   ├── proc_common_v3_00_a
│   │   │   │   ├── proc_common_v3_00_a.vdbl
│   │   │   │   └── proc_common_v3_00_a.vdbx
│   │   │   └── work
│   │   │   ├── work.vdbl
│   │   │   └── work.vdbx
│   │   ├── microblaze_v8_40_a
│   │   │   └── pcores
│   │   │   └── microblaze_v8_40_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── address_data_hit.vhd
│   │   │   ├── address_hit.vhd
│   │   │   ├── alu_bit.vhd
│   │   │   ├── alu.vhd
│   │   │   ├── barrel_shifter_gti.vhd
│   │   │   ├── barrel_shifter.vhd
│   │   │   ├── byte_doublet_handle_gti.vhd
│   │   │   ├── byte_doublet_handle.vhd
│   │   │   ├── cachehit_detect.vhd
│   │   │   ├── cache_interface.vhd
│   │   │   ├── cache_valid_bit_detect.vhd
│   │   │   ├── carry_and.vhd
│   │   │   ├── carry_compare_const.vhd
│   │   │   ├── carry_compare_mask.vhd
│   │   │   ├── carry_compare.vhd
│   │   │   ├── carry_equal.vhd
│   │   │   ├── carry_or.vhd
│   │   │   ├── comparator.vhd
│   │   │   ├── count_leading_zero.vhd
│   │   │   ├── data_flow_gti.vhd
│   │   │   ├── data_flow_logic_gti.vhd
│   │   │   ├── data_flow.vhd
│   │   │   ├── data_read_steering.vhd
│   │   │   ├── daxi_interface.vhd
│   │   │   ├── dcache_gti.vhd
│   │   │   ├── dcache.vhd
│   │   │   ├── dcache_wb.vhd
│   │   │   ├── debug.vhd
│   │   │   ├── decode_gti.vhd
│   │   │   ├── decode.vhd
│   │   │   ├── div_unit_gti.vhd
│   │   │   ├── div_unit.vhd
│   │   │   ├── dplb_interface.vhd
│   │   │   ├── dsp_module.vhd
│   │   │   ├── exception_registers_gti.vhd
│   │   │   ├── exception_registers.vhd
│   │   │   ├── find_first_bit.vhd
│   │   │   ├── fpu_addsub.vhd
│   │   │   ├── fpu_conv.vhd
│   │   │   ├── fpu_div.vhd
│   │   │   ├── fpu_mul.vhd
│   │   │   ├── fpu_sqrt.vhd
│   │   │   ├── fpu.vhd
│   │   │   ├── fsl_module.vhd
│   │   │   ├── gen_srlfifo.vhd
│   │   │   ├── iaxi_interface.vhd
│   │   │   ├── icache.vhd
│   │   │   ├── instr_mux.vhd
│   │   │   ├── interrupt_mode_converter.vhd
│   │   │   ├── iplb_interface.vhd
│   │   │   ├── jump_logic_gti.vhd
│   │   │   ├── microblaze_core.vhd
│   │   │   ├── microblaze_isa_be_pkg.vhd
│   │   │   ├── microblaze_primitives.vhd
│   │   │   ├── microblaze_types_pkg_body.vhd
│   │   │   ├── microblaze_types_pkg.vhd
│   │   │   ├── microblaze.vhd
│   │   │   ├── mmu_tlb.vhd
│   │   │   ├── mmu_types_pkg.vhd
│   │   │   ├── mmu_utlb_ram.vhd
│   │   │   ├── mmu_utlb.vhd
│   │   │   ├── mmu.vhd
│   │   │   ├── msr_reg_bit.vhd
│   │   │   ├── msr_reg_gti.vhd
│   │   │   ├── msr_reg.vhd
│   │   │   ├── mul_unit.vhd
│   │   │   ├── mux2_8.vhd
│   │   │   ├── mux4_8.vhd
│   │   │   ├── mux4.vhd
│   │   │   ├── mux_bus.vhd
│   │   │   ├── operand_select_bit.vhd
│   │   │   ├── operand_select_gti.vhd
│   │   │   ├── operand_select.vhd
│   │   │   ├── parity.vhd
│   │   │   ├── pc_bit.vhd
│   │   │   ├── pc_module_gti.vhd
│   │   │   ├── pc_module.vhd
│   │   │   ├── prefetch_buffer_gti.vhd
│   │   │   ├── prefetch_buffer.vhd
│   │   │   ├── pvr.vhd
│   │   │   ├── ram_module.vhd
│   │   │   ├── read_data_mux_gti.vhd
│   │   │   ├── register_file_bit.vhd
│   │   │   ├── register_file_gti.vhd
│   │   │   ├── register_file.vhd
│   │   │   ├── result_mux_bit.vhd
│   │   │   ├── result_mux.vhd
│   │   │   ├── shift_logic_bit.vhd
│   │   │   ├── shift_logic_gti.vhd
│   │   │   ├── shift_logic.vhd
│   │   │   ├── stack_protection.vhd
│   │   │   ├── stream_cache.vhd
│   │   │   ├── streaming_axi.vhd
│   │   │   ├── vec_mux.vhd
│   │   │   ├── victim_cache.vhd
│   │   │   ├── wb_mux_bit_gti.vhd
│   │   │   ├── wb_mux_gti.vhd
│   │   │   ├── zero_detect_gti.vhd
│   │   │   └── zero_detect.vhd
│   │   ├── proc_common_v3_00_a
│   │   │   └── pcores
│   │   │   └── proc_common_v3_00_a
│   │   │   └── hdl
│   │   │   └── vhdl
│   │   │   ├── counter_f.vhd
│   │   │   ├── family_support.vhd
│   │   │   ├── ipif_pkg.vhd
│   │   │   ├── proc_common_pkg.vhd
│   │   │   ├── pselect_f.vhd
│   │   │   └── pselect.vhd
│   │   ├── xil_670.in
│   │   ├── xil_670.out
│   │   ├── xil_946.in
│   │   └── xil_946.out
│   ├── microblaze_mcs_v1_2.ngc
│   ├── microblaze_mcs_v1_2.xco
│   ├── xlnx_auto_0_xdb
│   └── _xmsgs
├── microblaze_mcs_v1_2.lso
└── _xmsgs
└── xst.xmsgs

55 directories, 179 files

bests

Andrea

[herver]

Andrea, that looks like an OS issue.. Which Linux OS you're using?
Did you solve your issue?

[bwk]

Hello,

I know that this thread is quite old, but I didn't find any solution for this in the forum or on google when I had the same problem these days. So I would like to give a solution that is working for me. I am using Archlinux x86_64 with ISE 14.3.

Solution 1:

The first thing I found out was, that I was able to generate the core with coregen, when I generated a different core in advance. This means first I created for example a FIFO (FIFO Generator). After that I generated the Microblaze MCS and everything was fine. I only tried this solution with the coregen tool, not with the project navigator.

Solution 2:

As I don't find the first solution very feasible, I looked for another one. I found out that the files mb_bootloop_le.elf, microblaze_mcs_setup.tcl and system_template.tcl were missing during the creation of the core. So I modified the microblaze_mcs_gen_script.tcl in $XILINX/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/ to copy these three files into a tmp directory before the core is generated. This works for me in coregen and the project navigator.

file mkdir ./_cg/tmp/
file copy [concat $::env(XILINX)/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/mb_bootloop_le.elf] ./_cg/tmp/
file copy [concat $::env(XILINX)/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/microblaze_mcs_setup.tcl] ./_cg/tmp/
file copy [concat $::env(XILINX)/coregen/ip/xilinx/primary/com/xilinx/ip/microblaze_mcs_v1_2/system_template.tcl] ./_cg/tmp/

Regards,

bwk

[baberali]

HI,

I have the same problem on Ubuntu 64 bit edition. I am using xilinx ISE v14.7 and it uses microbalze v1_4. Can you upload your file you edited. Also I tried your solution both did not worked even I changed Microblaze version from V1_2 to v1_4.

regards

Ali 

[georgie]

Hi !

Same issue on Linux Mint 17.3 64-bit with ISE 14.7 and microblaze v1.4.

Could you please tell me where you inserted the lines you mention?

Best regards,

Georges

[payamfoug]

Thank you, that works for me on ubuntu 18.04 and ISE 14.7 with paths adapted to 14.7 version and micro-blaze 1.4 of course.