cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
clutch12
Explorer
Explorer
13,460 Views
Registered: ‎06-05-2014

problem with TDATA widths in AXI4 Stream Broadcaster

In Vivado 2014.2 the AXI4 stream broadcaster seems to have a tdata width on the output that is twice what it should be. Is this correct or is it a bug?

Untitled.png
0 Kudos
16 Replies
bwiec
Xilinx Employee
Xilinx Employee
13,433 Views
Registered: ‎08-02-2011

Most IP Integrator IP will automatically infer data widths from the cores driving them and propagate that to the output types. Try hooking the core into your system and see if it still is the same.
www.xilinx.com
zhuang123
Newbie
Newbie
13,029 Views
Registered: ‎01-13-2014

I met the same problem.

geoffjones
Visitor
Visitor
12,688 Views
Registered: ‎02-04-2014

 

Same problem. All of the output ports are twice the width that they should be.  I've tried leaving the settings on 'auto' and then hooking up the ports but they don't change. This is version 1.1 of the IP and I'm using Vivado 2014.2

 

broadcaster.png

0 Kudos
lcameron
Adventurer
Adventurer
12,392 Views
Registered: ‎02-14-2014

I'm getting something similar.   Perhaps I've missed something but I can't see how this block is even supposed to work at all?

 

It's not just the outputs (m_axis drivers) that are doubled, it's the input too for m_axis_tready.   However the doubling on this tready signal (only) is accounted for inside the block - looking at the synthesis, the two m_axis tready signals are AND'ed together and used to drive the s_axis tready.  In other words the broadcaster block only signals upstream that's it's ready when all of it's children are ready, this part makes perfect sense.

 

But the tlast, tuser etc. are different.   Each of these signals comes in from s_axis as a single signal input. The outputs to m_axis however are vectors, the doubling mentioned, and I suspect is actually one bit per output m_axis port.  But:  each s_axis signal is just wired straight to the first bit (only) of the m_axis output, meaning that it connects to the first child m_axis block only!  See the blue highlighted signals in the screenshot attached.  The other bits in the vector are just optimised away and tied low, so nothing works.  

 

Can someone from Xilinx please step in and confirm how exactly this block is supposed to be used, perhaps an example or testbench?  The docs for this (in the AXI stream suite) or the similar AXI Video Broadcaster don't have any detail of what is supposed to happen with all these signals.

 

 Screenshot from 2015-04-15 11:16:44.png

0 Kudos
alexkarnaukhov
Explorer
Explorer
11,757 Views
Registered: ‎09-25-2014

Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?
0 Kudos
guillaumebres
Scholar
Scholar
11,660 Views
Registered: ‎03-27-2014

I realized that by checking the pin/interface properties in the block design:
consider S[15:0] => ( M[15:0] = M00, M[31:16]=M01 ), the 16 bit input is duplicated into one LSB/MSB 32 word, which appears as two interfaces /M00 and /M01.
gw.
Embedded Systems, DSP, cyber
staceyrieck
Adventurer
Adventurer
7,218 Views
Registered: ‎03-03-2010


@alexkarnaukhov wrote:
Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?

No, it's not just that. The TVALIDs for each master also need to be adjusted. So its:

 

1) S_READY = M_READY_1 & M_READY_2

2) M_VALID_1 = S_VALID & M_READY_2

3) M_VALID_2 = S_VALID & M_READY_1

 

This deals with the case where one master is valid and the other isn't. Without #2 and #3 included, the valid master will see an asserted valid and an asserted ready, so it'll think it's a valid databeat. But it isn't, because the other master isn't ready. So it's necessary to drive the valid low when the opposite master isn't ready to deal with this case.

 

0 Kudos
me_sur
Visitor
Visitor
4,744 Views
Registered: ‎02-16-2018

I encountered similar issues in 2017.4

0 Kudos
pierlum
Voyager
Voyager
4,518 Views
Registered: ‎05-30-2017

Also in 2018.2

0 Kudos
johnmcd
Xilinx Employee
Xilinx Employee
4,235 Views
Registered: ‎02-01-2008

I have ran into slightly different issues regarding data width from the broadcaster. The simplest solution for me was to set the data width manually instead of relying on the 'auto' data width which uses parameter propagation to update the widths.

 

And my specific issue will also occur in 2018.3.

moons520
Visitor
Visitor
2,746 Views
Registered: ‎07-30-2017

I have the same problem。I hope s_axis_tdata[31:0], m_axis_tdata[23:0].

how to set this ip?)ZS{C9IX`M1PQ3$W%RH~Z)P.pngE]1{V)XI4`Z_JP0@)LX{SOK.png

0 Kudos
jfrye_wmi
Observer
Observer
2,378 Views
Registered: ‎08-19-2019

Can someone give a concise answer of what the purpose of this piece of logic is?

The guide says 

The AXI4-Stream Broadcaster provides a solution for replicating a single inbound AXI4-Stream interface into multiple outbound AXI4-Stream interfaces. Support for up to 16 outbound AXI4-Stream interfaces is provided. Each outbound interface also supports an optional remapping feature that allows you to select which TDATA (or TUSER) bits from the inbound interface are present on the TDATA (or TUSER) port of each outbound interface. A block diagram of the broadcaster is shown in Figure 2-1.

Why is it that when I have a single slave interface and two master interfaces, I am getting all signals on each master interface as double the width of the single slave when the master interfaces are configured to be the same width as the slave?

broadcaster.png

broadcasteroptions.png

I just want a piece of combinatorial logic to duplicate the input stream N times. This thing is so confusing, I will probably just write and RTL module that does it.

0 Kudos
huzaifasajids
Visitor
Visitor
2,104 Views
Registered: ‎12-09-2018

Encountered this problem in Vivado 18.1. Has anyone reached any solution?

0 Kudos
zblack
Visitor
Visitor
1,895 Views
Registered: ‎07-02-2018

I am having the same problem in Vivado 2019.1, is there a fix for this yet?

0 Kudos
Abady
Contributor
Contributor
887 Views
Registered: ‎08-11-2020

What is this super ultimate complex piece of logic no body knows any thing about, +6 years and still no answer ?!

 

I am using 2018.2 and I explored the forum and seems no one from Xilinx have answer about this duplication !

0 Kudos
vnesterov
Participant
Participant
408 Views
Registered: ‎12-10-2015

As @guillaumebres tried to explain above, the bus m_axis_tdata is a concatenation of all M_AXIS TDATA output buses. When you chose two output interfaces the m_axis_tdata width is double of your input width and if you chose three output then m_axis_tdata width will be triple of your input width and so on. Also in the IP configurator on the "Stream Splitting Options" you can check and remap what bits from input tdata bus the output buses are inheriting. 

Check the picture. The input's width is 32 and both M0 and M1 outputs TDATA are 32 width as well and m_axis_tdata width is 64.  All properties set to "auto".

Hope it helps.

broadcaster_explanation.png

Tags (1)
0 Kudos