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Explorer
Explorer
12,055 Views
Registered: ‎06-05-2014

problem with TDATA widths in AXI4 Stream Broadcaster

In Vivado 2014.2 the AXI4 stream broadcaster seems to have a tdata width on the output that is twice what it should be. Is this correct or is it a bug?

Untitled.png
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Xilinx Employee
Xilinx Employee
12,030 Views
Registered: ‎08-02-2011

Most IP Integrator IP will automatically infer data widths from the cores driving them and propagate that to the output types. Try hooking the core into your system and see if it still is the same.
www.xilinx.com
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Newbie
Newbie
11,626 Views
Registered: ‎01-13-2014

I met the same problem.

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Visitor
Visitor
11,285 Views
Registered: ‎02-04-2014

 

Same problem. All of the output ports are twice the width that they should be.  I've tried leaving the settings on 'auto' and then hooking up the ports but they don't change. This is version 1.1 of the IP and I'm using Vivado 2014.2

 

broadcaster.png

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Adventurer
Adventurer
10,989 Views
Registered: ‎02-14-2014

I'm getting something similar.   Perhaps I've missed something but I can't see how this block is even supposed to work at all?

 

It's not just the outputs (m_axis drivers) that are doubled, it's the input too for m_axis_tready.   However the doubling on this tready signal (only) is accounted for inside the block - looking at the synthesis, the two m_axis tready signals are AND'ed together and used to drive the s_axis tready.  In other words the broadcaster block only signals upstream that's it's ready when all of it's children are ready, this part makes perfect sense.

 

But the tlast, tuser etc. are different.   Each of these signals comes in from s_axis as a single signal input. The outputs to m_axis however are vectors, the doubling mentioned, and I suspect is actually one bit per output m_axis port.  But:  each s_axis signal is just wired straight to the first bit (only) of the m_axis output, meaning that it connects to the first child m_axis block only!  See the blue highlighted signals in the screenshot attached.  The other bits in the vector are just optimised away and tied low, so nothing works.  

 

Can someone from Xilinx please step in and confirm how exactly this block is supposed to be used, perhaps an example or testbench?  The docs for this (in the AXI stream suite) or the similar AXI Video Broadcaster don't have any detail of what is supposed to happen with all these signals.

 

 Screenshot from 2015-04-15 11:16:44.png

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Explorer
Explorer
10,354 Views
Registered: ‎09-25-2014

Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?
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10,257 Views
Registered: ‎03-27-2014

I realized that by checking the pin/interface properties in the block design:
consider S[15:0] => ( M[15:0] = M00, M[31:16]=M01 ), the 16 bit input is duplicated into one LSB/MSB 32 word, which appears as two interfaces /M00 and /M01.
gw.
Embedded Systems, DSP, cyber
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Adventurer
Adventurer
5,815 Views
Registered: ‎03-03-2010


@alexkarnaukhov wrote:
Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?

No, it's not just that. The TVALIDs for each master also need to be adjusted. So its:

 

1) S_READY = M_READY_1 & M_READY_2

2) M_VALID_1 = S_VALID & M_READY_2

3) M_VALID_2 = S_VALID & M_READY_1

 

This deals with the case where one master is valid and the other isn't. Without #2 and #3 included, the valid master will see an asserted valid and an asserted ready, so it'll think it's a valid databeat. But it isn't, because the other master isn't ready. So it's necessary to drive the valid low when the opposite master isn't ready to deal with this case.

 

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Visitor
Visitor
3,341 Views
Registered: ‎02-16-2018

I encountered similar issues in 2017.4

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Voyager
Voyager
3,115 Views
Registered: ‎05-30-2017

Also in 2018.2

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Xilinx Employee
Xilinx Employee
2,832 Views
Registered: ‎02-01-2008

I have ran into slightly different issues regarding data width from the broadcaster. The simplest solution for me was to set the data width manually instead of relying on the 'auto' data width which uses parameter propagation to update the widths.

 

And my specific issue will also occur in 2018.3.

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Visitor
Visitor
1,343 Views
Registered: ‎07-30-2017

I have the same problem。I hope s_axis_tdata[31:0], m_axis_tdata[23:0].

how to set this ip?)ZS{C9IX`M1PQ3$W%RH~Z)P.pngE]1{V)XI4`Z_JP0@)LX{SOK.png

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Observer
Observer
975 Views
Registered: ‎08-19-2019

Can someone give a concise answer of what the purpose of this piece of logic is?

The guide says 

The AXI4-Stream Broadcaster provides a solution for replicating a single inbound AXI4-Stream interface into multiple outbound AXI4-Stream interfaces. Support for up to 16 outbound AXI4-Stream interfaces is provided. Each outbound interface also supports an optional remapping feature that allows you to select which TDATA (or TUSER) bits from the inbound interface are present on the TDATA (or TUSER) port of each outbound interface. A block diagram of the broadcaster is shown in Figure 2-1.

Why is it that when I have a single slave interface and two master interfaces, I am getting all signals on each master interface as double the width of the single slave when the master interfaces are configured to be the same width as the slave?

broadcaster.png

broadcasteroptions.png

I just want a piece of combinatorial logic to duplicate the input stream N times. This thing is so confusing, I will probably just write and RTL module that does it.

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701 Views
Registered: ‎12-09-2018

Encountered this problem in Vivado 18.1. Has anyone reached any solution?

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Visitor
Visitor
492 Views
Registered: ‎07-02-2018

I am having the same problem in Vivado 2019.1, is there a fix for this yet?

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