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Participant
Participant
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Registered: ‎09-07-2017

qspi sample edage

hello all

      we use MT25QU512ABB1EW9-0SIT with zcu2eg, QSPI is sample at rise edage of clk ,but we capture the scope with Agilent MSO9254A,it is looks like sample at falling edage of clk ;

 

Test point:nearby pin of qspi

Porbe of CH2:Agilent N2796A

Probe of CH3:Agilent N2873A

qspi-D0-clk-3.jpg
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Scholar
Scholar
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Registered: ‎04-13-2015

Re: qspi sample edage

@zebulon

You should double check the setting for CPOL / CPHA in the QSPI control register.

That QSPI part samples on the rising edges and outputs on the trailing edges (CPOL0 / CPHA0)

It looks like the control register is set for CPOL1 / CPHA1 when it should be set for CPOL0 / CPHA0.

There is a very good explanation about CPOL / CPHA in Wikipedia

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

Be aware the QSPi controller only supports these two combinations: CPOL0 / CPHA0  or  CPOL1 / CPHA1

Regards

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Participant
Participant
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Registered: ‎09-07-2017

Re: qspi sample edage

thanks for your reply ! @ericv

As UG1087,we read the register of PH and POL at kernel.the value is 2b'00; As show in wiki; PH:POL = 2'b00 means sample at rising edage of the clk.

qspi.jpg

we do another test: capture the scope at u-boot stage.there is seem like sample at rising edage of clk.

 

 

 

 

qspi-lower-write-uboot.jpg
qspi-lower-read-uboot.jpg
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