regarding interrupt in vivado

[msh]

Hello, 

It is clear to me that I have to us concat block for the interrupt in the vivado but the xilinx sdk it apears only one signal 

eg: #defeine interrup 60

Whereas it is combination of two.  if I like to use this interrupts in my code then how can differentiate both ?

#define interrupt1 interrupt ??

#define interrupt2 interrup ??

thank you 

[debrajr]

You can check the xparameters.h file where in you would find separate Interrupt ID assigned to the IPs connected over concat IP. So, they are actually different.

[pvenugo]

Hi,

As mentioned above please check your xparameter.h which should have the respective two interrupts ID mentioned.

Would you like to share the file with me?

Regards

Praveen

[msh]

hi, 

In vivado I guess we have only one interrput port and we need to connected via connector (xconcate). here the MSB and LSB will be these two signal information.  

Therefore in the xparameter.h the defination appears as (which is only one not two)

/******************************************************************/

/* Definitions for Fabric interrupts connected to ps7_scugic_0 */
#define XPAR_FABRIC_DDR_ACCESS_CONTROLLER_0_SCAN_IRQ_INTR 61

/******************************************************************/

Please advice me how can use this single definition / or extract MSB and LSB from it for my interrupt.

NOTE: the intterrupt may be 16 bit long (not sure), as it can support 16 bit interrupts.

Thanks 

Best regards 

[debrajr]

It depends on what is connected to In0 & In1 of the Concat block? Are they connected to two different interrupt sources? Can you elaborate on the MSB & LSB query?

[pvenugo]

Hi,

#define XPAR_FABRIC_DDR_ACCESS_CONTROLLER_0_SCAN_IRQ_INTR 61 means ID number#61 is connected to In0.

Ideally INTR# 62 should be assigned for In1.

Regards

Praveen

[msh]

Hi, 

Thank you for you reply. 

But I donot understand why Vivado is not generating parameter for other pin. 

Both are connected to two different interrupt source.

Please suggest me what should I do, to correct it.

Thanks 

[msh]

Hi, 

Yes they both are connected to two different interrupts. one to int0 and other to int1. Also the signal to the PS7 is 1:0 form that mean two interrupt signal is accepted by processor but parameter donot have it.

Please see the picture, where LSB and MSB is mentioned.

Thank you 

Best regards 

[stephenm]

you can read the spi_status register to see exactly where the interrupts have been connected to. this will rule out any confusions or guesses. you can use the XSDB to to this. 

connect

fpga -f download.bit

targets -set -filter {name =~ "APU"}

source ps7_init.tcl

ps7_init

ps7_post_config

Trigger your interrupt

mrd 0xF8F01D04

mrd 0xF8F01D08

see the UG585 for how to read this

[msh · Accepted solution]

Hello, 

I have got the solution for the problem. 

The vivado cannot understand normal output port as interrupt, hence the output port need to be declared as interrupt in vivado port assignment during IP packaging. As shown in the below figure , then it will appear as SCAN_COMPLETED_O is shown in the figure.

[lbyoopp]

Thanks! It solved my problem.

BTW, it seems like that prior to 2015.4, there is no need to specify INTR port properties.

[jnievesr]

This solution didn't work for me in Vivado 2017.1. Am I missing something??

I modified my IP so the interrupt pin was ot type intr and then updated the design block with the latest IP. I then re ran synthesis, implementation, generated bitstream and exported Hwe. 

I generated a new bsp project and the VEC_ID is not there.

After that I added a second interrupt source from a xuartlite block and repeated the whole process.

The latest xparameters file inclueds the VEC_D for the uart but not for my IP

#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_UARTLITE_0_INTERRUPT_INTR

What do I need to do in order for it to work????

Thanks and Regards.