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nupur.ec
Observer
Observer
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Registered: ‎08-07-2019

s_axis_tready signal always low in mm2s IP.

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I am using mm2s IP with the XDMA IP configured as memory mapped PCIE endpoint. The m_xi of XDMA is connected to s_axi of mm2s IP. The stream signals of mm2s are further connected to a AXI-Stream DATA FIFO IP.
I am trying to simulate this design in the dma_test0 setup which sends (h2c) 128 bytes of data and then reads (c2h) this data back. I am able to see the h2c transfer happening all right but the c2h transfer is in error. On closer observation of signals, I see that the s_axis_tready signal from mm2s IP is not getting high. This signal is output from mm2s IP. This signal is further connected to the m_axis_tready of the FIFO IP and thus the FIFO data can not be read unless the mm2s s_axis_tready is high.

I could not find the conditions for this signal to be asserted in the documentation (pg102). Please suggest what am i missing in this design.

Regards,

Nupur

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florentw
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Registered: ‎11-09-2015

HI @nupur.ec 

What about the tvalid signal? It is important to note that according to the AXI spec, the slave can wait for the master to assert tvalid before asserting tready. The opposite is not true, tvalid cannot depend on tready.

Thus, the value of tvalid is the first point to check


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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434 Views
Registered: ‎11-09-2015

HI @nupur.ec 

What about the tvalid signal? It is important to note that according to the AXI spec, the slave can wait for the master to assert tvalid before asserting tready. The opposite is not true, tvalid cannot depend on tready.

Thus, the value of tvalid is the first point to check


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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