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Observer
Observer
3,763 Views
Registered: ‎02-16-2010

sos....Problem with MPMC_Clk0, InitDone remains LOW

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Hi everyone,

 

I am using EDK to communicate my IP core with DDR3 via MPMC using two NPI ports.

The board I am using is ML605.

By default, MPMC_Clk0 which is the MPMC system clock is set to 200MHz.

For some reason, my IP has to communicate with DDR3 under lower frequency (100MHz).

However, it doesn't work.

MPMC_InitDone remains low.... and the same with PIM0_InitDone and PIM1_InitDone.

It seems that the memory initialization is never finished.

 

What I have changed are MPMC_Clk0,  MPMC_Clk_Mem and MPMC_Clk_Rd_Base :

in MHS file:

before change the Clock frequency(default with MPMC_Clk0=200MHz):

 

BEGIN mpmc

.....

PORT MPMC_Clk0 = clk_200_0000MHzMMCM0  

PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0  

PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0  

PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase

....

END

 

BEGIN clock_generator  

PARAMETER INSTANCE = clock_generator_0  

PARAMETER C_CLKIN_FREQ = 200000000  

PARAMETER C_CLKOUT0_FREQ = 100000000  

PARAMETER C_CLKOUT0_PHASE = 0  

PARAMETER C_CLKOUT0_GROUP = MMCM0  

PARAMETER C_CLKOUT0_BUF = TRUE  

PARAMETER C_CLKOUT1_FREQ = 200000000  

PARAMETER C_CLKOUT1_PHASE = 0  

PARAMETER C_CLKOUT1_GROUP = MMCM0  

PARAMETER C_CLKOUT1_BUF = TRUE  

PARAMETER C_CLKOUT2_FREQ = 400000000  

PARAMETER C_CLKOUT2_PHASE = 0  

PARAMETER C_CLKOUT2_GROUP = MMCM0  

PARAMETER C_CLKOUT2_BUF = TRUE  

PARAMETER C_CLKOUT3_FREQ = 400000000  

PARAMETER C_CLKOUT3_PHASE = 0  

PARAMETER C_CLKOUT3_GROUP = MMCM0  

PARAMETER C_CLKOUT3_BUF = FALSE  

PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE  

PARAMETER C_PSDONE_GROUP = MMCM0  

PARAMETER C_EXT_RESET_HIGH = 1

PARAMETER HW_VER = 4.01.a  

PORT CLKIN = CLK_S  

PORT CLKOUT0 = clk_100_0000MHzMMCM0

PORT CLKOUT1 = clk_200_0000MHzMMCM0  

PORT CLKOUT2 = clk_400_0000MHzMMCM0  

PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase  

PORT PSCLK = clk_200_0000MHzMMCM0  

PORT PSEN = MPMC_DCM_PSEN  

PORT PSINCDEC = MPMC_DCM_PSINCDEC  

PORT PSDONE = MPMC_DCM_PSDONE  

PORT RST = sys_rst_s  

PORT LOCKED = Dcm_all_locked

END

 

after change the Clock frequency(with MPMC_Clk0=100MHz):

 

BEGIN mpmc

...

PORT MPMC_Clk0 = clk_100_0000MHzMMCM0  

PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0  

PORT MPMC_Clk_Mem = clk_200_0000MHzMMCM0

PORT MPMC_Clk_Rd_Base = DDR3_SDRAM_MPMC_Clk_Rd_Base

...

END

 

BEGIN clock_generator  

PARAMETER INSTANCE = clock_generator_0  

PARAMETER C_PSDONE_GROUP = MMCM0  

PARAMETER C_EXT_RESET_HIGH = 1  

PARAMETER HW_VER = 4.01.a  

PARAMETER C_CLKIN_FREQ = 200000000  

PARAMETER C_CLKOUT0_FREQ = 100000000

PARAMETER C_CLKOUT0_PHASE = 0  

PARAMETER C_CLKOUT0_GROUP = MMCM0  

PARAMETER C_CLKOUT0_BUF = TRUE  

PARAMETER C_CLKOUT1_FREQ = 200000000  

PARAMETER C_CLKOUT1_PHASE = 0  

PARAMETER C_CLKOUT1_GROUP = MMCM0  

PARAMETER C_CLKOUT1_BUF = TRUE  

PARAMETER C_CLKOUT2_FREQ = 200000000  

PARAMETER C_CLKOUT2_PHASE = 0  

PARAMETER C_CLKOUT2_GROUP = MMCM0  

PARAMETER C_CLKOUT2_BUF = FALSE  

PARAMETER C_CLKOUT2_VARIABLE_PHASE = TRUE  

PARAMETER C_CLKOUT3_FREQ = 50000000  

PARAMETER C_CLKOUT3_PHASE = 0  

PARAMETER C_CLKOUT3_GROUP = MMCM0  

PARAMETER C_CLKOUT3_BUF = TRUE  

PORT CLKIN = CLK_S  

PORT CLKOUT0 = clk_100_0000MHzMMCM0  

PORT CLKOUT1 = clk_200_0000MHzMMCM0  

PORT CLKOUT2 = DDR3_SDRAM_MPMC_Clk_Rd_Base  

PORT CLKOUT3 = my_custom_ip_0_Clock_50MHz

PORT PSCLK = clk_200_0000MHzMMCM0  

PORT PSEN = MPMC_DCM_PSEN  

PORT PSINCDEC = MPMC_DCM_PSINCDEC  

PORT PSDONE = MPMC_DCM_PSDONE  

PORT RST = sys_rst_s  

PORT LOCKED = Dcm_all_locked  

END

 

The relationship I found in the user guide is :

The MPMC_Clk_Rd_Base is the same frequency as MPMC_Clk_Mem, and should not be buffered to global routing.

The MPMC_Clk_Mem port drives the memory clock. MPMC_Clk0 is half the memory clock frequency and is synchronous to MPMC_Clk_Mem. Another port called MPMC_Clk_200MHz requires a 200 MHz clock to drive the IDELAY elements, but this clock can be asynchronous to all other clocks.

 

I have made the changes to MPMC_Clk0,  MPMC_Clk_Mem and MPMC_Clk_Rd_Base according to the user guide, but DDR3 is still not responding (InitDone remains low).

I am wondering if there is anything else that should be changed to make MPMC work at the lower frequency (100MHz).

Is there a frequency limitation to MPMC_Clk0...only 200MHz? 

 

Thanks for any hints.

 

 

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Xilinx Employee
Xilinx Employee
4,656 Views
Registered: ‎07-30-2007

Re: sos....Problem with MPMC_Clk0, InitDone remains LOW

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DDR3 has a minimum frequency of 300MHz. I suggest creating a design using the Base System Builder wizard to create the ML605 design to note the frequency ratios.

View solution in original post

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Highlighted
Xilinx Employee
Xilinx Employee
4,657 Views
Registered: ‎07-30-2007

Re: sos....Problem with MPMC_Clk0, InitDone remains LOW

Jump to solution

DDR3 has a minimum frequency of 300MHz. I suggest creating a design using the Base System Builder wizard to create the ML605 design to note the frequency ratios.

View solution in original post

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