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georgedu
Participant
Participant
5,014 Views
Registered: ‎04-03-2013

the problem of the pullup

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I take the exercise of the I2C .

By the BSB of XPS, i have the axi_iic .

and the code in SDK is the reapted_start_example .

My ucf is written as following:

# SCL
Net "Generic_IIC_Bus_Scl_pin" IOSTANDARD = LVCMOS25;
Net "Generic_IIC_Bus_Scl_pin" SLEW = SLOW;
Net "Generic_IIC_Bus_Scl_pin" DRIVE = 6;
Net "Generic_IIC_Bus_Scl_pin" PULLUP;

# SDA
Net "Generic_IIC_Bus_Sda_pin" IOSTANDARD = LVCMOS25;
Net "Generic_IIC_Bus_Sda_pin" SLEW = SLOW;
Net "Generic_IIC_Bus_Sda_pin" DRIVE = 6;
Net "Generic_IIC_Bus_Sda_pin" PULLUP;

 

in simulaion ,i just see the signal of the SCLand SDA are both  Z

is it because I don't use the pull_up resistor on the board?if so,what is the purpose of the PULLUP command in UCF

or is it because i don't connect the  slave?if so ,the master is supposed to send the first byte of the slave's address

 

the attachment is the result of simulaiton .

thanks for your help 

 

simulation.png
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gszakacs
Instructor
Instructor
6,009 Views
Registered: ‎08-14-2007

If this is a behavioral simulation, it won't show the pullup because it doesn't know about

your UCF file.  Behavioral simulation only uses the VHDL sources, no other external

files including constraints.  If you want to see a pull-up in the simulation, you should do

it in the test bench.  In Verilog this would look like:

 

pullup (SDA);

pullup (SCL);

 

In VHDL you need to assign a weak 1 to the SDA and SCL nets.  If you look through

the forums for other threads on I2C pullup you should see an example of this.  If you

do a post-translate simulation, then the pullups should be in the simulation model

and you should see the SDA and SCL signals go from strong 0 to weak 1.

-- Gabor

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4 Replies
gszakacs
Instructor
Instructor
6,010 Views
Registered: ‎08-14-2007

If this is a behavioral simulation, it won't show the pullup because it doesn't know about

your UCF file.  Behavioral simulation only uses the VHDL sources, no other external

files including constraints.  If you want to see a pull-up in the simulation, you should do

it in the test bench.  In Verilog this would look like:

 

pullup (SDA);

pullup (SCL);

 

In VHDL you need to assign a weak 1 to the SDA and SCL nets.  If you look through

the forums for other threads on I2C pullup you should see an example of this.  If you

do a post-translate simulation, then the pullups should be in the simulation model

and you should see the SDA and SCL signals go from strong 0 to weak 1.

-- Gabor

View solution in original post

hgleamon1
Teacher
Teacher
5,004 Views
Registered: ‎11-14-2011

To add to what Gabor has already written, to add a simulating pullup in the testbench code in VHDL, you should write this:

 

sda <= 'H';

scl <= 'H';

 

Note these are continuous assignments, not part of any process.

 

Another thing, I wouldn't try to use the FPGA pullup (as written in your UCF) to handle the deassertion of the signals. It is too weak to meet the requirements of IIC. You must use an external pullup on the board, approximately 3k for a 3.3V signal level.

 

Regards,

 

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle
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georgedu
Participant
Participant
4,994 Views
Registered: ‎04-03-2013

thanks for both of your's help 

hha

 

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ranjaninaidu_22
Observer
Observer
1,268 Views
Registered: ‎09-26-2018

Hi Georgedu,

 

I am facing the same problem, could have a solution for this. I tried implementing I2C using Microblaze, using the following ways to get output

  1. Tried pulling up in test bench
  2. In UCF we mentioned the constraints properly.
  3. Example codes in directory didn’t work either.

 

Any solution from your end would be helpful.

 

Thanks in Advance 

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