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Registered: ‎04-18-2019

ultrascale A53 L2 cache

Does the A53 L2 cache can be allocated between different cores , like zynq 7000 by cache lockdown?

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Moderator
Moderator
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Registered: ‎07-31-2012

Hi dfx28@ntesec.com.cn ,

Like Zynq-7000 device in Zynq US+ L2 SCU arbitrates L2 request between cores.

Regards

Praveen


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Scholar
Scholar
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Registered: ‎04-13-2015

dfx28@ntesec.com.cn 

Lockdown can be done as specified in section D.4.4.10 of

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

It is "implementation defined" and I didn't see anything related to this in the UltraScale+ Register Map (lots of registers so I may have missed it).

@pvenugo : you've indicated the SCU handles this. Could you pinpoint the registers to set up as they are not A53 native?

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