11-20-2017 01:41 AM
Hi there !
I'm looking for a way to write in slcr register from PL (if it is possible !).
For now I run one baremetal application on each CPU. CPU0 is in charge to start CPU1.
I'm able to reset CPU1 from CPU0, But I would like to reset CPU1 from PL.
Sequence would be :
- unlock register
- reset CPU0
- lock register
Do you have any ideas ?
11-29-2017 09:01 AM
There is no method for the PL to have access to the PS register space that I'm aware of. I think another way to do what you have in mind is to have the PL issue an interrupt to CPU0, then in that interrupt have CPU0 reset CPU1.
11-30-2017 04:20 AM
Hi glena, thank you for answer.
I found some clue that is should be possible, don't know exactly how though.
In ug585 (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) I found this :
Note: Unlike the POR or system resets, when the user applies a software reset to a single processor, the user must stop the associated clock, de-assert the reset, and then restart the clock. During a system or POR reset, hardware automatically takes care of this. Therefore, a CPU cannot run the code that applies the software reset to itself. This reset needs to be applied by the other CPU or through JTAG or PL. Assuming the user wants to reset CPU0, the user must to set the following fields in the slcr.A9_CPU_RST_CTRL (address 0x000244) register in the order listed:
1. A9_RST0 = 1 to assert reset to CPU0
2. A9_CLKSTOP0 = 1 to stop clock to CPU0
3. A9_RST0 = 0 to release reset to CPU0
4. A9_CLKSTOP0 = 0 to restart clock to CPU0
So it seems to be possible.
In SLCR section in ug585 (p 114), it says : The System-Level Control registers (SLCR) consist of various registers that are used to control the PS behavior. These registers are accessible via the central interconnect using load and store instructions.
So i'm gessing I need to find a way to talk with the PS central interconnect.
I assume we can connect to the central interconnect through AXI slave GP port.
So I need to have an AXI master in PL to be able to talk with this port and write the right values to the right address.
But I don't exactly know how to do and where to begin to achieve this goal.
Not sure the flow is correct though.
Do you have any inputs ?
11-30-2017 05:56 AM
I think my interrupt solution is a much better method. What you are trying to do is not a supported method.
11-30-2017 06:54 AM
This is not a solution for me. The PL MUST apply the reset to the CPU.
Maybe you know other way to reset CPU(s) only from PL.
Thank you anyways.