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xilinxbert
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Registered: ‎02-17-2009

xps_mch_emc data bus mapping

Hi all,

 

I have a strange issue with the xps_mch_emc (2.00.a) IP. This IP is connected to a PLBv46 bus.

 

I have a 16 bit data bus towards my external FLASH device. I read and write to the IP from a Microblaze, which means that I use 32 bit access. Somehow, the data must be mapped to the 16 bit FLASH data bus.

 

The strange thing is, that this mapping is different for writing and reading.

 

 

Here is my read function:

 

UINT32 Flash_Rd(UINT32 FlashAddr)
{

    /* Convert the address */
    UINT32 PlbAddr =  (FLASH_0_BASE_ADDR + (FlashAddr << 2));   
    /* Read the data from the PLB bus. */
    return((UINT32)(XIo_In32(PlbAddr) ));

} 

 

And my write function:

 

static void Flash_Wr(UINT32 FlashAddr, UINT32 Value)
{

    /* Convert the address */
    UINT32 PlbAddr =  (FLASH_0_BASE_ADDR + (FlashAddr << 2));
    /* Write the data to the PLB bus. */
    XIo_Out32(PlbAddr , (Value << 16));
}

 

Notice that I shift the data to write by 16 bit ( << 16 ), while I read the data without shifting. This means that the data I write is mapped to the left side of the bus ( 0xFFFFXXXX ), and the data to read on the right ( 0xXXXXFFFF ).

 

Don't get me wrong, this code is working. I just want to understand what's happening here, and I want to equalize both functions (without shifts).

 

Finally, here are my settings for the IP:

 

BEGIN xps_mch_emc
 PARAMETER INSTANCE = flash
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MEM0_BASEADDR = 0x50000000
 PARAMETER C_MEM0_HIGHADDR = 0x5FFFFFFF
 PARAMETER C_NUM_BANKS_MEM = 2
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_MEM1_WIDTH = 16
 PARAMETER C_MEM1_BASEADDR = 0x60000000
 PARAMETER C_MEM1_HIGHADDR = 0x6FFFFFFF
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_THZCE_PS_MEM_0 = 70000
 PARAMETER C_THZOE_PS_MEM_0 = 70000
 PARAMETER C_TWC_PS_MEM_0 = 150000
 PARAMETER C_TWP_PS_MEM_0 = 120000
 PARAMETER C_TCEDV_PS_MEM_0 = 150000
 PARAMETER C_TAVDV_PS_MEM_0 = 150000
 PARAMETER C_THZCE_PS_MEM_1 = 70000
 PARAMETER C_THZOE_PS_MEM_1 = 70000
 PARAMETER C_TWC_PS_MEM_1 = 150000
 PARAMETER C_TWP_PS_MEM_1 = 120000
 PARAMETER C_TCEDV_PS_MEM_1 = 150000
 PARAMETER C_TAVDV_PS_MEM_1 = 150000
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
 BUS_INTERFACE SPLB = plb_bus
 PORT Mem_DQ_T = flash_Mem_DQ_T
 PORT Mem_DQ_O = flash_Mem_DQ_O
 PORT Mem_DQ_I = flash_Mem_DQ_I
 PORT Mem_A = flash_Mem_A
 PORT Mem_WEN = flash_Mem_WEN
 PORT Mem_OEN = flash_Mem_OEN
 PORT Mem_CEN = flash_Mem_CEN
 PORT MCH_PLB_Clk = sys_clk
 PORT RdClk = sys_clk
END

 

 

Who can tell me what's going on here?

 

Kind regards,

Bert

 

 

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23 Replies
prateek_bhatt
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Registered: ‎08-21-2008

Hello.

Use the 16 bit API of the processor.

That is XIo_In16() and XIo_Out16() and see what happens.

Also how many address lines your memory has. 

 

According to my calculation your memory has 24 addr lines and 16 data lines (32 MB memory capacity).

And if you are using one memory only then the addressing becomes

[7:30] <=> [23 :0] 

where [7 :30] are the address lines of EMC controller to be used out of 32 address lines and [23:0] are the address lines of the memory device.

And the above mapping is reversed to counter big endian format.

If you have followed the above addressing then its OK.

Also try to run TestApp_Memory.c

It should pass all the tests. 

Message Edited by prateek_bhatt on 08-28-2009 04:00 AM
Best of luck.
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xilinxbert
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Registered: ‎02-17-2009

Hi Prateek_bhatt,

 

I tried to use the 16 bit IO functions, but the result is not surprising.

 

When I use the XIo_Out16, writing is fine. This I would expect, because internally the data is shifted 16 bit (like I did manually with the XIo_Out32 function). For the same reason, the XIo_In16 fails. The read data is shifted 16 bit to the right. While it was OK in the 32 bit format, it now leaves all zeroes. The data mismapping must be situated at a lower level.

 

The address mapping is indeed like you describe it.

 

I believe that the test app will fail, because it doesn't use any CFI commands. But that's no problem, since my own software is capable of testing the FLASH.

 

Kind regards,

Bert

 

 

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prateek_bhatt
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Registered: ‎08-21-2008

Hello.

I have used intel strata flash js28f256 p30.

This has 24 addr lines and 16 data lines (32 MB capacity) with the blocking facility.

I used the addressing i told you and i never had to bother about any shifting and also i used 16 bit processor's API.

Best of luck.
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xilinxbert
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Registered: ‎02-17-2009

Hi,

 

And which emc controller did you use?

 

Kind regards,

Bert

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prateek_bhatt
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Registered: ‎08-21-2008

xps_mch_emc controller.

Instance name :: Generic external memory

Verison 10.1.03 

Also did on 9.1 and 9.2 before. 

Best of luck.
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xilinxbert
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Registered: ‎02-17-2009

Can I maybe see your MHS file, to see if I made any errors there?
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prateek_bhatt
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Registered: ‎08-21-2008

Sure, why not.
Best of luck.
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prateek_bhatt
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Registered: ‎08-21-2008

But tell me one thing that if your FLASH is 32 MB then how come the difference between the baseaddr and highaddr is 0x0FFFFFFF in your MHS file.

It should be 0x01FFFFFF. Check it out.

According to your MHS file the memory capacity is 256 MB which is incorrect. 

Best of luck.
--
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xilinxbert
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Registered: ‎02-17-2009

My FLASH isn't 32MB, it's larger. This also would not have created any problem, as long as you don't read/write outside the real FLASH boundaries.

 

I think btw, I have found the problem.

 

In you design, you are using the Mem_DQ pin, to connect the data bus to the FLASH. I have used the Mem_DQ_I, Mem_DQ_O and Mem_DQ_T. This is the only difference.

 

In your case you could never have a difference in mapping, because din and dout share the same signal. In my case, there are two signals.

 

I'm running a test build now to test this.

 

 

Bert

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xilinxbert
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Registered: ‎02-17-2009

That didn't solve the problem.
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mgkiller
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Registered: ‎09-25-2010

hi

 

i also have some difficult in operating my FLASH(intel 256p30) via xps_mch_emc ; and i have token two weeks and make great efforts to work for it but in vain. So now would you send me your " intel strata flash js28f256 p30" project to me for reference.

yourApp.mhs and yourApp.c  will be enough!

 

Kind regards,

mgkiller

 

 

 

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prateek_bhatt
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Hello mgkiller,

I think i am logging into this site after 8 months or so since u directly asked me. I am no more in this field now. Bur still whatever i have worked so far i have a record of it. So i am attaching MHS file and C file in this. Have a look. Till my last day i worked on 10.1.03 version. The after-versions i don't know at all. There will be one MHS file and three C files all required for the project in my case. Use them accordingly in yours.

Best of luck.
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prateek_bhatt
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The first C file....

Best of luck.
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prateek_bhatt
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The Second C file....

Best of luck.
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prateek_bhatt
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The third C file....

Best of luck.
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mgkiller
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Registered: ‎09-25-2010

hi prateek_bhatt ,

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mgkiller
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Registered: ‎09-25-2010

hi

  

i am full of gratitude for your helping. i also want to know how do you map the Flash(intel256P30) to the emc IP core?  since the data bus of this flash is x16bit width.

is that right? what my mapping is( refered to xilinx ML505 demo board,flash is little endian and EDK is big endian)

ADDR BUS:

emc_Mem_A[30]-----------flash_Mem_A1 (there is no A0 pin in 256P30,A1 is the least significant address  bit.   )  emc_Mem_A[29]-----------flash_Mem_A2

emc_Mem_A[28]-----------flash_Mem_A3

.

.

.

emc_Mem_A[8]-----------flash_Mem_A23

emc_Mem_A[7]-----------flash_Mem_A24

DATA BUS:

emc_Mem_DQ[15]------flash_Mem_DQ[0]

emc_Mem_DQ[14]------flash_Mem_DQ[1]

.

.

.

emc_Mem_DQ[1]------flash_Mem_DQ[14]

emc_Mem_DQ[0]------flash_Mem_DQ[15]

 

but when use XIo_Out16( (FlashBaseAddr + (0x1<<1)), 0x60 )  or XIo_In16(FlashBaseAddr + (0x1<<1))to address my Flash, i found  flash_Mem_A1( the least significant address  bit) isn't  set  '1'  but flash_Mem_A2  in ChipScope .  is that mean i should map emc_Mem_A[29]-----------flash_Mem_A1 and than emc_Mem_A[6]-----------flash_Mem_A24? and how did you map the flash?  and are the address bus and data bus reverse need?

 

Kind regards,

mgkiller

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prateek_bhatt
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Actually i was expecting this question from you. In your post u said that only MHS and C file will be enuf so i changed my mind and didn't give you UCF file. Well the answer you are looking for is in the xps_mch_emc datasheet. Right click on your emc controller and select datasheet of the controller. Now in the datasheet somewhr in between u will find "mapping flash to your EMC controller"...although i don't exactly remember. Actually it has to be calculated as far as mapping is concerned through the parameters mentioned in the datasheet of the emc controller and and the timing parameters mentioned in the 28f256p30 datasheet.

Also remember to counter the big endian format in EDK you have to fill UCF in reverse order. Like the zeroth number data line of the controller has to be mapped to FPGA pin number assigned to the last data line(15th in ur case) of the controller and so on. I have given comments in data and address pins. They will help u understand big endian format.Always remember SRAM and FLASH require calculation so its important.

To cross check your calculation i am attaching the UCF file for your reference. But make sure u calculate it before using the mapping done in my UCF file otherwise everytime you will ask for mapping.

Best of luck.
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prateek_bhatt
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Referring to page number 21 of XPS MCH EMC v3.01a datasheet...

The calculation will be like this......

 

MW=16
DW=16
MAW=24
AU=8
AS=0
HAW=32

 

So according to connection formula of address mapping mentioned we have.....

Controllers (HAW-MAW-AS : HAW-AS-1) <=> devices (MAW-1 : 0)

So address mapping will be,

xps_mch_emc controllers [8:31] <=> 28f256p30 device [23:0]

That means,

8th pin of your controllers address bus maps to last address of your device...

9th pin of your controllers address bus maps to second last address of your device and so on...

Leave the 0 to 7 address lines of your controller unmapped.

 

Also remember that since you have taken care of the shift here in the UCF so u don't have to shift in the C file. Write and read directly from the address. Hope it helps.

Best of luck.
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mgkiller
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Registered: ‎09-25-2010

hi prateek_bhatt ,

 

I have solved the problem, thank you for your generous help!

 I hope I can continue to receive your support!

 

Kind regards,

 mgkiller

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mgkiller
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hi dylan ,

 

I have solved the problem, thank you for your generous help!

 I hope I can continue to receive your support!

 

Kind regards,

 mgkiller

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Registered: ‎02-16-2011

Perfect match. Thank you, for your generosity.
Keep on doing...

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blunchy
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Hi, I cannot see why you need the "udelay" function in your code.

Thanks a lot for all the information you provided.

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