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ar2019
Contributor
Contributor
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Registered: ‎02-06-2020

zynq MPSoC PS PLL clocks phase alignment

Hi all,

 

I have a project with zynq MPSoC Ultrascale+ FPGA. I need 2 clocks phase aligned to each other. I selected PL clocks into PL fabric. 

clock_config.png 

 

I assumed that PS PLL has the same datasheet as any FPGA PLL. According to ug572 they both should be aligned. 

ug572.png

However when I simulate the design I see that they are not. I added clock wizard to generate same clocks inside of PL. And got 2 clocks are aligned. 

simulation.png

I would like to know if simulation is what to expect from PS IOPLL.

 

Thank you.

 

 

 

 

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4 Replies
avrumw
Guide
Guide
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Registered: ‎01-23-2009

The PS PLL is not the same as all the other PLLs/MMCMs in the FPGA. The PS PLL is a simple PLL for generating one or more frequencies on the PS_CLK pins based on the oscillator that must be provided to the PS (since the PS needs a clock, and in the Zynq, the PS can run without any resources from the PL - in fact the PS programs the PL).

The different clock outputs of the PS are specifically mentioned as being not phase aligned in any way to each other - they are frequency references only (I don't remember where the documentation states this, but I remember that since it was odd, I made some inquiries to verify that this was really true). 

So, if you need multiple phase related clocks, you must use a PL PLL (or better yet, an MMCM). You can drive the PS_CLK to the CLKIN of an MMCM (I don't remember if it needs a clock buffer or not), and from that MMCM you can generate multiple related clocks.

Avrum

ar2019
Contributor
Contributor
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Registered: ‎02-06-2020

Thank you for the quick reply. This is what I was looking for but failed to find after spending tons of time.

 

You don't need the buffer as it seems. It is coming into the fabric from through one. At least how routed design looks like.

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

Be aware, if you want two clocks from the same MMCM/PLL to be in phase at the destinations, you need to put the two clock nets in the same CLOCK_DELAY_GROUP - see this post on the CLOCK_DELAY_GROUP property.

Avrum

ar2019
Contributor
Contributor
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Registered: ‎02-06-2020

Thank you very much! This is very useful!

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