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Visitor
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Registered: ‎01-12-2015

zynq axi --- programmable logic---- storage communication

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Hello everyone, I'm new here.  I am going to be doing  a project involving the zc706 and a storage device.  Currenly I'm still in the planning/research stage and there are some things I dont really understand.  If anyone has the time to answer any of these questions that would greatly be appreciated

 

The project will involve building a controller in the Programmable logic to interface between the ARM system and the storage device.

 

1)  AXI3 or AXI4.  I'm not familiar with AXI.  Am I restricted to one or the other using the zc706 board?

 

2) Device selection.  How are devices selected in AXI? It seems like there are multiple devices that can be written/read from. Is it part of the actual address or is there a separate signal somewhere I'm not seeing? 

 

3) Sector addressing.  It seems that AXI has a 32-bit address signal and it is byte addressed.  Is this correct?  If this is true, how would I go about addressing my storage device which has more than 4GB of data?  Furthermore, it appears that axi3 only supports burst lengths of 16.  I need to address sectors of 512 bytes on my storage device.  If i used 32bit axi that means i would need 128 burst length.

 

I think it's pretty clear I'm not fully understanding AXI.  I've been reading the IHI0022E_amba_axi_and_ace_protocol_spec.pdf datasheet but it's not quite getting through to me.

If anyone knows a good link to nice axi tutorials/examples I would appreciate those as well.

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Teacher
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Registered: ‎03-31-2012
1) Zynq ports to PL are AXI3 but Xilinx has conversion IP which translates between the two so you can make your IP AXI4.
2) Devices(slaves) are selected based on their address.
3) AXI is not limited to 32 bit address but Zynq has 32 bit processors so it's limited to 32 bits. You can always create an IP which has a programmable base address which can point to different 4G block.
As to burst length: Zynq interfaces are AXI3 but some are also 64 bits so you can make an AXI3 master and write to DDR at 128 bits at a time. In AXI address width is not identical to data width. Zynq has two HP ports which are 8 byte wide each so you can write 16 bytes at a time to DDR with a burst of 16 (actually there are 4 HP ports but only two ports of DDR are accessible to HP so it makes sense to use only 2 of them).
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Teacher
Teacher
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Registered: ‎03-31-2012
1) Zynq ports to PL are AXI3 but Xilinx has conversion IP which translates between the two so you can make your IP AXI4.
2) Devices(slaves) are selected based on their address.
3) AXI is not limited to 32 bit address but Zynq has 32 bit processors so it's limited to 32 bits. You can always create an IP which has a programmable base address which can point to different 4G block.
As to burst length: Zynq interfaces are AXI3 but some are also 64 bits so you can make an AXI3 master and write to DDR at 128 bits at a time. In AXI address width is not identical to data width. Zynq has two HP ports which are 8 byte wide each so you can write 16 bytes at a time to DDR with a burst of 16 (actually there are 4 HP ports but only two ports of DDR are accessible to HP so it makes sense to use only 2 of them).
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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Visitor
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Registered: ‎01-12-2015

I wanted to expand on my question 3)  Does Xilinx provide some IP that will automatically do the "block selection" or "windowing" for me? 

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