cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sanghyun_kim
Observer
Observer
381 Views
Registered: ‎02-17-2020

zynq axi timing

Jump to solution

amba axi protocol specification explains axi signal ARVALID like as

Read address valid. This signal indicates, when HIGH, that the read address and control
information is valid and will remain stable until the address acknowledge signal,
ARREADY, is high.
1 = address and control information valid
0 = address and control information not valid.

 i can't understand this sentence

remain stable until the address acknowledge signal

means ARVALID must stable between clock edge, or other timing.

because there is no acknowledge signal (ARACK?, etc...) 

 

also i can't find timing information on vivado axi interconnect manual .

 

what is correct timing keep ARVALID signal to high.

 

 

Tags (2)
1 Solution

Accepted Solutions
abouassi
Moderator
Moderator
315 Views
Registered: ‎03-25-2019

Hi @sanghyun_kim,

The phrase should be read to the end:

will remain stable until the address acknowledge signal, ARREADY, is high.

This means the acknowledge signal in this case is "ARREDY".


From the AXI spec (plz double check that you are using the latest version of the spec):
"Once VALID is asserted it must remain asserted until the handshake occurs, at a rising clock edge at which VALID and READY are both asserted."

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

0 Kudos
2 Replies
abouassi
Moderator
Moderator
316 Views
Registered: ‎03-25-2019

Hi @sanghyun_kim,

The phrase should be read to the end:

will remain stable until the address acknowledge signal, ARREADY, is high.

This means the acknowledge signal in this case is "ARREDY".


From the AXI spec (plz double check that you are using the latest version of the spec):
"Once VALID is asserted it must remain asserted until the handshake occurs, at a rising clock edge at which VALID and READY are both asserted."

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

0 Kudos
sanghyun_kim
Observer
Observer
262 Views
Registered: ‎02-17-2020

also i missed this.

ACLK Clock source Global clock signal. All signals are sampled on the rising edge of the global clock.

 all signal sampled on the pos-edge.

slave may assert arready after pos-edge.