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Explorer
Explorer
4,748 Views
Registered: ‎11-11-2013

zynq custom ip implementation error: [Drc 23-20] Rule violation (IOCNT-2) Number of HP/HR IOs

 

 

HI there,

 

I tried to build a custom ip with AXI lite slave and AXI master interface. The ip project is working in synthesis, but failed in implementipn. 

 

The error msg shows :

[Drc 23-20] Rule violation (IOCNT-2) Number of HP/HR IOs - The design contains 230 unplaced High Range-only I/O ports while the target device, xc7z020clg484-1, has 200 remaining available High Range I/O pins. To correct this issue:
1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.
2. Check the top-level ports of the design to ensure the correct number of ports are specified.
3. Consider design changes to reduce the number of High Range I/O pins needed.

 

Since the IO ports of the IP are not mapped to real ios of the zynq, it should be fine with more io than number available on hte chip. How can I figure this out?

Thank you.

Sam

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Xilinx Employee
Xilinx Employee
4,734 Views
Registered: ‎08-02-2007

Hi,

 

Depending on the device that you have choose(XC7z020) in this case, there are only a few set of HP/HR IO's available.

The IP that is created by the CIP might be having IO's depending on the IP configuration.

So you will have to remove some of the IP's example ports from connecting I/O for the example design to fit in the target device.

 

I would suggest that you look at the wrapper of the IP created and figure out the signals that should be going to the IO level.

 

--Hem

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Explorer
Explorer
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Registered: ‎11-11-2013

 

 

Hi Hem

Thanks for your reply. 

Could you plz specify more details for the operation of "look at the wrapper of the IP created and figure out the signals that should be going to the IO level"?

Appreciate it.

Sam

 

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Explorer
Explorer
4,705 Views
Registered: ‎11-11-2013

 

Some more details of the issue:

 

The custom ip I built is very simple. It is created by CIP and  only contains an AXI lite and AXI full interfaces. (see the plot attached.) 

 

IP Error.JPG

 

 

I found a similar issue posted here:

http://www.xilinx.com/support/answers/60059.html#linkedARRecords

 

But I didn't understand how to figure it out:

"User will need to remove some of the IP's example ports from connecting I/O for the example design to fit in the target device.  For this small device it is more reasonable to use post-crc functionality than SEM IP."

 

And I have two questions:

1). Is it feasible to create a custom ip with an AXI lite and AXI full interfaces?

2). If it is feasible for such custom ip, how to remove the  Rule violation (IOCNT-2)? The solution applied in the post is not clear to me. Please specify the solution in more details. 

Thank you very much.

Sam

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Explorer
Explorer
4,649 Views
Registered: ‎11-11-2013

 

Any idea? Plz....

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Adventurer
Adventurer
4,640 Views
Registered: ‎08-08-2008

Hi,

  I think you might have tried to place and route a design with only a single IP of yours in the block diagram, and with all that AXI bus signals dangling.  Otherwise how would your design end up with 230 I/O signals?

  Have you looked at Vivado Embedded design tutorial UG940?

 

Neo

  

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Teacher
Teacher
4,631 Views
Registered: ‎03-31-2012

did you make a block diagram which includes your IP and a zynq ? your IP has a master port and a slave port. In the block diagram you need to connect both these to some interfaces. Can you show what your chip block diagram looks like?
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