zynq7000 not getting correct DRAM results when doing a cache flush

[jcwill585]

I'm writing to DRAM from the PL and when I go to read in the PS most of the time the results are wrong.  I do a cacheflush before the read and sometimes I get the correct data and sometimes I don't.  I have another program running on core0.  How do I fix this?  

u64 value;

u32 DRAM_Acess_Consistency_addr = 0x20000000;

u64* DRAM_Acess_Consistency = (u64*)(DRAM_Acess_Consistency_addr);

Xil_DCacheFlushRange(DRAM_Acess_Consistency_addr , 8*32);
for(int i=0; i<32; i++) {
value = DRAM_Acess_Consistency[i];
}

[jcwill585 · Accepted solution]

A cache invalidate should be performed when getting DRAM data written from PL.  Here's the code:

u64 value;

u32 DRAM_Acess_Consistency_addr = 0x20000000;

u64* DRAM_Acess_Consistency = (u64*)(DRAM_Acess_Consistency_addr);

Xil_DCacheInvalidateRange(DRAM_Acess_Consistency_addr , 8*32);
for(int i=0; i<32; i++) {
value = DRAM_Acess_Consistency[i];
}