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Contributor
Contributor
1,308 Views
Registered: ‎09-13-2018

32 bit reads and writes from PS to PL DDR4

I am missing something fundamental.  In the past on zynq 7 parts I am able to generate a MIG, connect it to the PS.  Then read and write to any part of that memory from the PS using /dev/mem as long as I allowed 32 bit access in the MIG.

On my zynqMP system I am trying to do the same.  I have a 512 bit interface with the MIG, interconnect interfaces the MIG to the HPM0_FPD port at 128 bits wide.  I am using devmem command to try to read and write and then read again a memory address, but i am failing to consistantly manipulate the memory on a 32 bit basis.

I wanted to pass this simple test before I dive into DMA IP.  Is it not possible to manipulate DDR4 memory on this sort of bus on a 32 bit basis?

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12 Replies
Scholar jg_bds
Scholar
1,220 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

Assuming your DDR interface has and properly uses DM (Data Mask) signals, you should be able to manipulate data on an 8-bit basis. (Very wasteful... but possible.) A 512-bit-wide data port on a user interface to a MIG implies a 64-bit-wide DDR interface, which should be accompanied by 8 DM signals. 

Is this a custom board? Are the DM signals connected between the MIG within the ZynqMP, and the DDR chips? Some dastardly HW designers pull these signals at the DDR chips to save routing space, which means a whole burst--64 bytes--must be written at a time. 

Is your DDR memory comprised of 4-bit DDR devices? Such devices do not have DM pins, so they also would need to be written as a whole burst.

Are the DDR Mode Registers being used to re-purpose DM signals for DBI functionality? If so, you've lost the DM functionality, and memory must be written as a whole burst.

-Joe G.

 

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Contributor
Contributor
1,193 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

See my responses.

Assuming your DDR interface has and properly uses DM (Data Mask) signals, you should be able to manipulate data on an 8-bit basis. (Very wasteful... but possible.) A 512-bit-wide data port on a user interface to a MIG implies a 64-bit-wide DDR interface, which should be accompanied by 8 DM signals. 

Is this a custom board? 

No.  HiTech Global z920.

Are the DM signals connected between the MIG within the ZynqMP, and the DDR chips?

Yes

Some dastardly HW designers pull these signals at the DDR chips to save routing space, which means a whole burst--64 bytes--must be written at a time. 

Not the case in this instance. 

Is your DDR memory comprised of 4-bit DDR devices? 

No, 2 ranks of 8 bit devices.

Such devices do not have DM pins, so they also would need to be written as a whole burst.

Are the DDR Mode Registers being used to re-purpose DM signals for DBI functionality? 

Hmm maybe.  I need to follow up and learn about this DBI functionality!

If so, you've lost the DM functionality, and memory must be written as a whole burst.

 

Thanks for the tips and pointers.

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Contributor
Contributor
1,170 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

Definately using DM/DBI pins in DM mode.

Still stumped.

 

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Scholar jg_bds
Scholar
1,165 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

PL-based MIG on Z920 is wired-up to support ECC. Is ECC involved?

What kind of interface are you using to access the MIG: AXI or User Interface?

-Joe G.

 

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Contributor
Contributor
1,156 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

It is wired up for ECC, but no ECC is involved.

 

I am using AXI to interface to the 512 bit interface.

I am using The M_AXI_HPM0_FPD PS interface with 128 bits to interface through an AXI interconnect to the MIG IP.

 

I recently watched the read/write transactions on the AXI bus with a debug core, and all looked normal with mask/strobe bits being set but the data being read back from the MIG core was incorrect and exactly what devmem on the command line was reporting.

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Scholar jg_bds
Scholar
1,150 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

So your controller is set for no ECC, and you're using a non-ECC DIMM?

What, exactly, is the nature of the corrupted read data?

Can you share ILA traces of the AXI transactions?

-Joe G.

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Contributor
Contributor
1,127 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

So your controller is set for no ECC, and you're using a non-ECC DIMM?

Yes

--

Today I went backwards and ran my tests with a 4GB SODIMM instead of 16GB.   Works perfectly through all of my mem tests.  Definately MIG and 16GB SODIMM related

For instance.

I am using devmem.


root@test20181217:/media/card/coreydevdir# devmem 0x1000000000
0x00000000
root@test20181217:/media/card/coreydevdir# devmem 0x1000000000 w 0xDEADBEEF
root@test20181217:/media/card/coreydevdir# devmem 0x1000000000
0x0000EFDE
root@test20181217:/media/card/coreydevdir# devmem 0x1000000000
0xEFDEADBE
root@test20181217:/media/card/coreydevdir# devmem 0x1000000000
0xEFDEADBE

 

Consecutive reads have different data.  With no writes in between.

Then i move to a new memory address.

root@test20181217:/media/card/coreydevdir# devmem 0x1100000000
0xEFDEADBE
root@test20181217:/media/card/coreydevdir# devmem 0x1100000000
0x508114C2
root@test20181217:/media/card/coreydevdir# devmem 0x1100000000
0x508114C2

 

I can share traces.  I currently do not see anything wrong with the bus as the bad data is coming out of the MIG/DDR4 incorrectly when I read.  The command line is working to print what i see in the read traces.

 

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Scholar jg_bds
Scholar
1,115 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

You've been changing DIMMs...?

A MIG is created to work with a specific arrangement of memory devices, or a particular DIMM. You generally can't switch DIMMs. The MIG doesn't have an I2C interface to query a DIMM and make adjustments to its behavior or configuration based on the DIMM's needs.

You should determine which DIMM your MIG was created for, and only test against that DIMM.

-Joe G.

 

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Contributor
Contributor
1,095 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

No, of course every time i changed a DIMM i changed the mig.  I wanted to isolate the problem to the MIG/DDR4 and make sure that some other piece of my PS/PL was not the problem.

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Scholar jg_bds
Scholar
1,084 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

Is the DIMM configuration file you're using (for the DIMM that exhibits problems) a canned Xilinx configuration? Or is it a custom one you/your company made?  Has the configuration been used to create a working MIG for that DIMM on any other board?

-Joe G.

 

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Contributor
Contributor
1,078 Views
Registered: ‎09-13-2018

Re: 32 bit reads and writes from PS to PL DDR4

It is new and untested.  I have been using answer records and forum posts along with the micron datasheet fo the components on the DIMM to form the configuration file.  Been double checking my initial design of that file to figure out what I am missing.

 

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Scholar jg_bds
Scholar
1,072 Views
Registered: ‎02-01-2013

Re: 32 bit reads and writes from PS to PL DDR4

 

Then it's definitely worth investigating that configuration file. Your methodology and MIG creation appear correct, since you can get your system working "as-expected" with a different DIMM. 

-Joe G.

 

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